Computer system

• US 6,606,678 B1
• Filed: 06/28/2000
• Issued: 08/12/2003
• Est. Priority Date: 06/29/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Nobutaka
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): CHUNG TRANS, XUONG MY
• Application Number:
  US09/605,399
• Time in Patent Office: 1,140 Days
• Field of Search: 710/305, 710/306, 710/311, 710/312, 710/313, 710/314, 710/300, 710/301, 710/302, 710/303, 710/304
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

In this invention, the bus of a computer body is connected to the bus of an expansion unit through a serial interface so as to implement connection wirings in the form of a serial cable. A PCI-PCI bridge for connecting a primary PCI bus to a secondary PCI bus comprises two physically isolated controllers, i.e., a primary PCI serial transfer controller implemented on the PC body side and a secondary PCI serial transfer controller implemented on the docking station side. The two controllers are connected to each other through serial LVDS lines. Transactions are exchanged between the primary PCI bus and the secondary PCI bus by serial transfer between the primary PCI serial transfer controller and the secondary PCI serial transfer controller.

Claims

1. A computer system comprising:

first and second buses respectively constituted by multiple-bit-width parallel transmission paths;

a first controller connected to said first bus;

a second controller connected to said second bus; and

a serial transmission path interposed between said first and second controllers,

wherein said first and second controllers exchange a command, address, and data of a transaction from one of said first and second buses to the other bus through said serial transmission path, each of said first and second controllers comprising;

a bus interface means which operates in synchronous with the same first clock signal as that used by a device on a corresponding one of the first and second buses to exchange a transaction with the corresponding bus, and

serial transfer means that operates in synchronous with a second clock signal asynchronous to the first clock signal so as to execute serial transfer through the serial transmission path.

2. A computer system according to claim 1, wherein said first and second controllers logically constitute one unit.

3. A computer system according to claim 1, wherein said serial transmission path includes a plurality of serial transmission path.

4. A system according to claim 1, wherein said first and second controllers share a configuration address space assigned by one IDSEL signal.

5. A system according to claim 1, wherein said first controller has a first configuration register indicating an operation environment, said second controller has a second configuration register indicating an operation environment, and identical pieces of environmental setting information are respectively set in the first and second configuration registers.

6. A system according to claim 5, wherein identical pieces of environmental setting information are respectively set in the first and second configuration registers by copying the environmental setting information in the first configuration register to the second configuration register.

7. A system according to claim 1, wherein the serial transmission path includes at least one differential signal line pair.

8. A system according to claim 7, wherein each of said first and second controllers comprises:

means for encoding information required for transfer from a corresponding one of said first and second buses to the other bus into m-bit (m>

n) code sequences in units of m-bit information words, and

means for converting the m-bit (m>

n) code sequence into serial data and outputting the serial data to the differential signal line pair.

9. A system according to claim 8, wherein said encoding means encodes information words into code sequences with the ratios for the numbers of 1s to the numbers of 0s are substantially equal.

10. A system according to claim 8, wherein each of said first and second controllers comprises:

means for receiving serial data output to the differential signal line pair and decoding an m-bit (m>

n) code sequence into an n-bit information word, and

means for converting the decoded n-bit information word into parallel data to be output to said first or second bus.

11. A system according to claim 1, wherein the serial transmission path includes at least one differential signal line pair, and a transformer is inserted in each differential signal line pair.

12. A system according to claim 11, wherein each of said first and second controllers comprises:

means for converting information required for transfer from a corresponding one of said first and second buses to the other bus, from parallel data into serial data, and

means for converting each binary data constituting the serial data into ternary data including a first state in which a current flows in said transformer in a positive direction, a second state in which a current flows in said transformer in a negative direction, and a third state in which no current flows in said transformer, and outputting the ternary data to the differential signal line pair.

13. A system according to claim 12, wherein said each of said first and second controllers comprises:

means for detecting ternary data on the differential signal line pair and converting the detected ternary data into binary data, and

means for converting serial data constituted by the converted binary data into parallel data to be output to said first or second bus.

14. A computer system comprising:

first and second buses respectively constituted by multiple-bit-width parallel transmission paths;

a first controller connected to said first bus;

a second controller connected to said second bus;

a serial transmission path interposed between said first and second controllers,

wherein said first and second controllers exchange a command, address, and data of a transaction from one of said first and second buses to the other bus through said serial transmission path;

wherein said first controller comprises first bus interface means for exchanging a transaction with the first bus;

wherein said second controller comprises second bus interface means for exchanging a transaction with the second bus; and

wherein said first and second bus interface means operate in synchronous with the first and second clock signals respectively which are asynchronous to each other.

15. A computer system according to claim 14, wherein said first and second controllers logically constitute one unit.

16. A computer system comprising:

first and second buses respectively constitute by multiple-bit-width parallel transmission paths;

a first controller connected to said first bus;

a second controller connected to said second bus;

a serial transmission path interposed between said first and second controllers,

wherein said first and second controllers exchange a command, address, and data of a transaction from one of said first and second buses to the other bus through said serial transmission path;

wherein the serial transmission path comprises a full duplex channel including at least one pair of unidirectional serial transmission paths whose signal transmission directions are opposite to each other; and

wherein each of the unidirectional serial transmission paths includes a serial data line for serially transferring the command, address, and data, and a clock signal line for transferring corresponding clock signals.

17. A computer system according to claim 16, wherein said first and second controller logically constitute one unit.