Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
First Claim
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1. A parallel hardware-based multithreaded processor comprises:
- a plurality of microengines that support multiple hardware threads, each microengine comprising;
a plurality of program counters;
with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time;
a general purpose processor that coordinates system functions, the general purpose processor loading microcontrol programs for the plurality of microcontrol engines; and
a first bus to couple the general purpose processor to the plurality of microengines.
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Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
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Citations
17 Claims
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1. A parallel hardware-based multithreaded processor comprises:
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a plurality of microengines that support multiple hardware threads, each microengine comprising;
a plurality of program counters;
with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time;
a general purpose processor that coordinates system functions, the general purpose processor loading microcontrol programs for the plurality of microcontrol engines; and
a first bus to couple the general purpose processor to the plurality of microengines. - View Dependent Claims (2, 3, 4, 5, 6, 7)
a static random access memory controller that optimizes memory references based upon whether the memory references are read references or write references.
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4. The processor of claim 1 wherein each of the plurality of microengines use the program counters to enable hardware-based context swapping amongst the plurality of threads that are independently executable within each of the microengines.
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5. The processor of claim 1 further comprising an bus interface that couples the processor to a communication bus.
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6. The processor of claim 1 further comprising a bus interface that couples the processor to a computer system bus.
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7. The processor of claim 1 further comprising:
an internal bus arrangement to couple shared resources in the processor to the plurality of microengines.
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8. A parallel hardware-based multithreaded processor comprises:
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a plurality of microengines that support multiple hardware threads, each microengine comprising;
a plurality of program counters;
with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time;
a general purpose processor that coordinates system functions, the general purpose processor loading microcontrol programs for the plurality of microcontrol engines;
a media access controller device coupled to an interface; and
a first bus to couple the general purpose processor, the plurality of microengines, and the interface.
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9. A parallel hardware-based multithreaded processor comprises:
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a general purpose processor that coordinates system functions; and
a plurality of microengines that support multiple hardware threads, the microengines comprising;
a control store to store a microprogram;
the microprogram loadable by the general purpose processor;
controller logic including an instruction decoder and program counter unit to execute the microprogram; and
a plurality of program counters;
with the microengines maintaining states associated with the program counters to enable a plurality of sets of threads of computer instructions to be simultaneously active on each of the microengines while one actually executes at any one time.- View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
a translator device that translates requests from the general purpose processor to the microengines; and
a first bus to couple the general purpose processor to the plurality of microengines; and
a second bus to couple the general purpose processor to the memory control system.
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15. The processor of claim 9 further comprising an internal bus arrangement to couple shared resources in the processor to the plurality of microengines wherein the shared resources comprise:
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a memory controller for controlling access to low latency memory;
a memory controller for controlling an access to high bandwidth memory;
a bus interface for controlling access to a communications bus; and
a bus interface for controlling access to a computer bus.
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16. The processor of claim 9 wherein the processor supports global signaling to each of the microengines.
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17. The processor of claim 16 wherein the global signaling is available to each thread to permit each thread in each microengine.
Specification