Method and apparatus for decoding of a serially concatenated block and convolutional code

• US 6,606,724 B1
• Filed: 01/28/2000
• Issued: 08/12/2003
• Est. Priority Date: 01/28/2000
• Status: Expired due to Term

• Current Assignee: MaxLinear Communications, LLC (f/k/a Entropic Communications, LLC) (Maxlinear Incorporated)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Eidson, Donald Brian, Krieger, Abraham
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/492,962
• Time in Patent Office: 1,292 Days
• Field of Search: 714/755, 714/786, 714/794, 714/795
• US Class Current: 714/755
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/2936 comprising an outer Reed-Solomon code and an inner convolutional code
• CPC Class Codes: H03M 13/2948 Iterative decoding H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2972 Serial concatenation using convolutional component codes
• CPC Class Codes: H03M 13/3776 using a re-encoding step during the decoding process
• CPC Class Codes: H03M 13/3994 using state pinning or decision forcing, i.e. the decoded sequence is forced through a particular trellis state or a particular set of trellis states or a particular decoded symbol

Abstract

A decoder having a first decoder providing first decoded data. A deinterleaver is included for deinterleaving the first decoded data. A second decoder provides second decoded data based on the deinterleaved first decoded data. The second decoder provides at least one decode status signal indicative of second decoder operations. A pipeline decoder unit is included that is coupled to the second decoder. The pipeline decoder unit includes an encoder that receives the second decoded data and provides forced decision data, a multiplexer, and a third decoder that provides pipelined decoded data. The multiplexer is responsive to the at least one decode status signal to selectively constrain the pipelined decoded data to be at least partially dependent on the forced decision data.

Claims

1. A decoding system for decoding serially concatenated encoded symbols comprising:

a first serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the first serial concatenated code decoder configured to receive as an input data derived from the serially concatenated encoded symbols, and the hard input outer decoder of the first serial concatenated code decoder configured to output hard bit decisions and corresponding status indicators; and

a first replicable unit comprising;

a first interleaver, an inner encoder, and a mapper coupled in series, wherein the first interleaver is configured to interleave data derived from the hard bit decisions, and the mapper is configured to map encoded information from the inner encoder into high-reliability soft values;

a second interleaver and a modified inner encoder coupled in series, wherein the second interleaver is configured to interleave data derived from the status indicators, and the modified inner encoder is configured to produce selection values;

a multiplexor for selecting, responsive to the selection values, between outputting data derived from the serially concatenated encoded symbols as delayed and the high reliability soft values; and

a second serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the second serial concatenated code decoder configured to receive as an input data derived from the output of the multiplexor, and the hard input outer decoder of the second serial concatenated code decoder configured to output hard bit decisions and corresponding status indicators.

2. The system of claim 1 further comprising a second replicable unit which is a replica of the first replicable unit and has first and second interleavers, wherein the first interleaver of the second replicable unit is configured to interleave data derived from the hard bit decisions produced within the first replicable unit, and the second interleaver of the second replicable unit is configured to interleave data derived from the status indicators produced within the first replicable unit.

3. The system of claim 2 wherein the first and second replicable units are pipelined replicas of one another.

4. The system of claim 2 wherein the first and second replicable units are instantiations of a unit shared over different iterations.

5. The system of claim 2 wherein the first and second serial concatenated code decoders are instantiations of a decoder shared over different iterations.

6. The system of claim 1 wherein the soft input inner decoders of the first and second serial concatenated code decoders are Viterbi decoders.

7. The system of claim 1 wherein the hard input outer decoders of the first and second serial concatenated code decoders are block decoders.

8. The system of claim 7 wherein the block decoders are Reed Solomon decoders.

9. The system of claim 1 wherein the inner encoder of the first replicable unit is configured with a plurality of XOR gates, and the modified inner encoder of the first replicable unit is a replica of the inner encoder of the first replicable unit with one or more of the plurality of XOR gates thereof replaced with AND gates.

10. A decoding system for decoding serially concatenated encoded symbols comprising:

a first serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the first serial concatenated code decoder configured to receive as an input data derived from the serially concatenated encoded symbols, and the hard input outer decoder of the first concatenated code decoder configured to output hard bit decisions and corresponding status indicators; and

a first replicable unit comprising;

a first interleaver configured to interleave data derived from the hard bit decisions;

a second interleaver configured to interleave data derived from the status indicators; and

a second serial concatenated code decoder comprising a soft input inner decoder, a de-interleaver, and a hard input outer decoder coupled in series, the soft input inner decoder of the second serial concatenated code decoder configured to (1) receive as inputs data derived from the interleaved status indicators and interleaved hard bit decisions, and data derived from the serial concatenated encoded symbols as delayed, and (2) selectively render state or branch metrics as undesirable responsive to the data derived from the interleaved status indicators, and the hard input outer decoder of the second serial concatenated code decoder configured to output hard bit decisions and corresponding status indicators.

11. The system of claim 10 further comprising a second replicable unit which is a replica of the first replicable unit and has first and second interleavers, wherein the first interleaver of the second replicable unit is configured to interleave data derived from the hard bit decisions produced within the first replicable unit and the second interleaver of the second replicable unit is configured to interleave data derived from the status indicators produced within the first replicable unit.

12. The system of claim 11 wherein the first and second replicable units are pipelined replicas of one another.

13. The system of claim 11 wherein the first and second replicable units are instantiations of a unit shared over different iterations.

14. The system of claim 10 wherein the soft input inner decoders of the first and second serial concatenated code decoders are Viterbi decoders.

15. The system of claim 10 wherein the hard input outer decoders of the first and second serial concatenated code decoders are block decoders.

16. The system of claim 15 wherein the block decoders are Reed Solomon decoders.

17. The system of claim 10 wherein the first and second serial concatenated code decoders are instantiations of a decoder shared over different iterations.

18. A decoding system for decoding serially concatenated encoded symbols comprising:

first serial concatenated code decoding means for receiving as an input data derived from the serially concatenated encoded symbols, and outputting bard bit decisions and corresponding status indicators; and

a first replicable unit comprising;

first interleaving means for interleaving data derived from the hard bit decisions;

second interleaving means for interleaving data derived from the status indicators; and

second serial concatenated code decoding means for outputting hard bit decisions and corresponding us indicators responsive to the interleaved data from the first and second interleaving means.

19. The system of claim 18 wherein the first replicable unit further comprises:

inner encoding means for encoding data derived from the interleaved data provided by the first interleaving means and mapping means for mapping data derived from the encoded data provided by the inner encoding means into high reliability soft values;

modified inner encoding means for producing selection values responsive to the interleaved data from the second interleaving means; and

multiplexing means for selecting, responsive to the selection values, between outputting data derived from the serially concatenated encoded symbols as delayed and the high reliability soft values;

wherein the second serial concatenated code decoding means outputs hard bit decisions and corresponding status indicators responsive to data derived from the output of the multiplexing means.

20. The system of claim 19 wherein the inner decoding means is configured with a plurality of XOR gates, and the modified inner encoding means of the first replicable unit comprises the inner encoding means of the first replicable unit with one or more of the XOR gates thereof replaced with AND gates.

21. The system of claim 18 wherein the second serial concatenated code decoding means selectively renders state or branch metrics as undesirable responsive to the interleaved data from the second interleaving means, and also outputs hard bit decisions and corresponding status indicators responsive to the interleaved data from the first interleaving means and,data derived from the serial concatenated encoded symbols as delayed.

22. The system of claim 18 further comprising a second replicable unit wherein the first interleaving means thereof interleaves data derived from the hard bit decisions produced within the first replicable unit and the second interleaving means thereof interleaves data derived from the status indicators produced within the first replicable unit.

23. The system of claim 22 wherein the first and second replicable units are pipelined replicas of one another.

24. The system of claim 22 wherein the first and second replicable units are instantiations of the same unit shared over different iterations.

25. The system of claim 18 wherein the first and second serial concatenated code decoding means are instantiations of the same decoding means shared over different iterations.

26. A method of decoding serially concatenated encoded symbols comprising:

outputting hard bit decisions and corresponding status indicators responsive to data derived from the serially concatenated encoded symbols; and

performing the following substeps in a first replicable unit;

interleaving data derived from the hard bit decisions;

interleaving data derived from the status indicators; and

outputting hard bit decisions and corresponding status indicators responsive to data derived from the interleaved status indicators, the interleaved hard bit decisions, and the serial concatenated encoded symbols as delayed.

27. The method of claim 26 further comprising performing the following substeps in the first replicable unit:

encoding data derived from the interleaved hard bit decisions;

mapping the encoded data into high reliability soft values;

encoding data derived from the interleaved status indicators to produce selection values;

selecting, responsive to the selection values, between outputting data derived from the serially concatenated encoded symbols as delayed and the high reliability values; and

outputting hard bit decisions and corresponding status indicators responsive to the selected data.

28. The method of claim 26 further comprising performing the following substeps in the first replicable unit:

selectively rendering state or branch metrics in a soft input inner decoder as undesirable responsive to the interleaved status indicators; and

outputting from the soft input inner decoder hard bit decisions and corresponding status indicators responsive to the interleaved hard bit decisions and the serial concatenated encoded symbols as delayed.

29. The method of claim 26 further comprising performing the following substeps in a second replicable unit:

interleaving data derived from the hard bit decisions produced within the first replicable unit;

interleaving data derived from the status indicators produced within the first replicable unit; and

outputting hard bit decisions and corresponding status indicators responsive to data derived from the interleaved status indicators and the interleaved hard bit decisions as produced within the first replicable unit, and the serial concatenated encoded symbols as delayed.

30. The method of claim 29 wherein the first and second replicable units are pipelined replicas of one another.

31. The method of claim 29 wherein the first and second replicable units are instantiations of the same unit shared over different iterations.