Integrated circuit device having an embedded heat slug

• US 6,607,928 B1
• Filed: 09/28/2000
• Issued: 08/19/2003
• Est. Priority Date: 12/30/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Paniccia, Mario J., Eiles, Travis M.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Brock, II, Paul E
• Application Number:
  US09/676,268
• Time in Patent Office: 1,055 Days
• Field of Search: 438/15, 438/16, 438/122, 438/584, 438/26, 438/108, 438/977, 257/706, 257/707, 257/720, 257/712, 257/713, 257/717, 257/796
• US Class Current: 438/16
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10158 at the passive surface

Abstract

An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and a backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

Claims

1. A method comprising:

cooling a portion of an integrated circuit located on a frontside surface of a semiconductor substrate, said semiconductor substrate having a backside surface opposite said frontside surface, said portion comprising a high power density region of said integrated circuit;

creating an opening in said backside surface of said semiconductor substrate adjacent said portion of said integrated circuit, wherein a distance between said backside surface of said semiconductor substrate and a floor of said opening is greatest directly above said high power density region;

depositing a thermally conductive, infrared transparent material in said opening so that the thermally conductive material is embedded in close proximity directly above the high power region; and

planarizing said backside surface of said semiconductor substrate after depositing said thermally conductive material in said opening.

2. The method of claim 1 further comprising thermally coupling said thermally conductive material to a heat sink.

3. The method of claim 1 wherein said opening extends from said backside surface of said semiconductor substrate to a point located within 100 microns above said portion of said integrated circuit.

4. The method of claim 1 wherein creating said opening includes chemically etching said backside surface of said semiconductor substrate.

5. The method of claim 1 wherein creating said opening includes etching said backside surface of said semiconductor substrate using a gas-assisted laser etching system.

6. The method of claim 1 wherein creating said opening includes etching said backside surface of said semiconductor substrate using a focused ion beam.

7. The method of claim 1 wherein creating said opening includes milling said backside surface of said semiconductor substrate.

8. The method of claim 1 further comprising planarizing said backside surface of said semiconductor substrate after depositing said thermally conductive material in said opening.

9. The method of claim 1 wherein said thermally conductive material has a thermal conductivity greater than the thermal conductivity of said semiconductor substrate.

10. The method of claim 1 wherein said thermally conductive material comprises diamond.

11. The method of claim 1 wherein depositing said thermally conductive material comprises a chemical vapor deposition process.

24. The method of claim 2 wherein the heat sink comprises a heat pipe.

12. A method comprising:

creating an embedded heat slug in a semiconductor substrate having an integrated circuit device on a frontside surface thereof, said semiconductor substrate having a backside surface opposite said frontside surface;

creating an opening in said backside surface of said semiconductor substrate adjacent a portion of said integrated circuit, said portion comprising a high power density region of said integrated circuit, wherein a distance between said backside surface of said semiconductor substrate and a floor of said opening is greatest directly above said high power density region;

depositing a thermally conductive, infrared transparent material, in said opening so that the thermally conductive material is embedded in close proximity directly above the high power region; and

planarizing said backside surface of said semiconductor substrate after depositing said thermally conductive material in said opening.

13. The method of claim 12 further comprising thermally coupling said thermally conductive material to a heat sink.

14. The method of claim 13 wherein the heat sink comprises a heat pipe.

15. The method of claim 12 wherein said opening in said backside surface extends from said backside surface of said semiconductor substrate to a point located within 100 microns above said portion of said integrated circuit.

16. The method of claim 12 wherein creating said opening includes chemically etching said backside surface of said semiconductor substrate.

17. The method of claim 12 wherein creating said opening includes etching said backside surface of said semiconductor substrate using a gas-assisted laser etching system.

18. The method of claim 12 wherein creating said opening includes etching said backside surface of said semiconductor substrate using a focused ion beam.

19. The method of claim 12 wherein creating said opening includes milling said backside surface of said semiconductor substrate.

20. The method of claim 12 further comprising planarizing said backside surface of said semiconductor substrate after depositing said thermally conductive material in said opening.

21. The method of claim 12 wherein said thermally conductive material has a thermal conductivity greater than the thermal conductivity of said semiconductor substrate.

22. The method of claim 12 wherein said thermally conductive material comprises diamond.

23. The method of claim 12 wherein depositing said thermally conductive material comprises a chemical vapor deposition process.

25. A method comprising:

cooling a portion of an integrated circuit located on a frontside surface of a semiconductor substrate, said semiconductor substrate having a backside surface opposite said frontside surface, wherein cooling said portion of an integrated circuit includes creating an opening in said backside surface of said semiconductor substrate adjacent a portion of said integrated circuit, said portion of said integrated circuit comprising a high power density region of said integrated circuit, wherein a distance between said backside surface of said semiconductor substrate and a floor of said opening is greatest directly above said high power density region, embedding a thermally conductive, infrared transparent material in said opening to fill said opening so that the thermally conductive, infrared transparent material is in close proximity directly above the high power region, and planarizing said backside surface of said semiconductor substrate after embedding said thermally conductive material in said opening.

26. The method of claim 25 further comprising thermally coupling said thermally conductive material to a heat sink.

27. The method of claim 26 wherein said heat sink comprises a heat pipe.

28. The method of claim 25 wherein said opening extends from said backside surface of said semiconductor substrate to a point located within 100 microns above said portion of said integrated circuit.

29. The method of claim 25 wherein creating said opening includes chemically etching said backside surface of said semiconductor substrate.

30. The method of claim 25 wherein creating said opening includes etching said backside surface of said semiconductor substrate using a gas-assisted laser etching system.

31. The method of claim 25 wherein creating said opening includes etching said backside surface of said semiconductor substrate using a focused ion beam.

32. The method of claim 25 wherein creating said opening includes milling said backside surface of said semiconductor substrate.

33. The method of claim 25 wherein said thermally conductive material has a thermal conductivity greater than the thermal conductivity of said semiconductor substrate.

34. The method of claim 25 wherein said thermally conductive material comprises diamond.

35. The method of claim 25 wherein depositing said thermally conductive material comprises a chemical vapor deposition process.

36. The method of claim 25 further comprising passing an air flow over a finned heat sink thermally coupled to said backside surface.

37. The method of claim 25 further comprising attaching the thermally conductive material to said backside surface of said semiconductor substrate and thermally coupling said thermally conductive material to a heat sink.

38. The method of claim 37 wherein said heat sink comprises a heat pipe.

39. The method of claim 25 further comprising thermally coupling the thermally conductive material to a heat spreading plate by a heat pipe.

40. A method comprising:

choosing a location to embed a thermally conductive, infrared transparent heat slug in a semiconductor substrate having an integrated circuit device on a frontside surface thereof, said semiconductor substrate having a backside surface opposite said frontside surface, and wherein choosing said location to embed said heat slug includes selecting a high power density region;

creating an opening in said backside surface of said semiconductor substrate adjacent said integrated circuit device, wherein a distance between said backside surface of said semiconductor substrate and a floor of said opening is greatest directly above said high power density region;

embedding said heat slug in said opening to fill said opening so that the heat slug is in close proximity directly above the high power density region; and

planarizing said backside surface of said semiconductor substrate after embedding said heat slug in said opening.

41. The method of claim 40 wherein choosing said location to embed said heat slug includes selecting a location that will require optical probing.