High voltage vertical conduction superjunction semiconductor device

• US 6,608,350 B2
• Filed: 12/07/2000
• Issued: 08/19/2003
• Est. Priority Date: 12/07/2000
• Status: Expired

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M., Sridevan, Srikant
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US09/732,401
• Publication Number:
  US 20020070418A1
• Time in Patent Office: 985 Days
• Field of Search: 257/339, 257/341, 257/331
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A high voltage vertical conduction semiconductor device has a plurality of deep trenches or holes in a lightly doped body of one conductivity type. A diffusion of the other conductivity type is formed in the trench walls to a depth and a concentration which matches that of the body so that, under reverse blocking, both regions fully deplete. The elongated trench or hole is filled with a dielectric which may be a composite of nitride and oxide layers having a lateral dimension change matched to that of the silicon. The filler may also be a highly resistive SIPOS which permits leakage current flow from source to drain to ensure a uniform electric field distribution along the length of the trench during blocking.

Claims

1. A high voltage vertical conduction superjunction semiconductor device comprising:

a body of one conductivity type;

a plurality of spaced vertical trenches formed into the upper surface of said body;

a diffusion of the other conductivity type formed into the interior surface of said plurality of said trenches;

a MOSgated structure connected to the top of said body and to the top of each of said diffusions;

the thickness and concentration of said diffusion and the width and concentration of said body being matched to insure substantially full depletion of said diffusion and body when blocking voltage is applied to said body;

wherein said MOSgated structure comprises a base of the other conductivity type extending across the top of said body, a plurality of spaced source regions of the one conductivity type diffused into said base, a plurality of second trenches in the top of said base and between respective pairs of said trenches, a gate oxide lining the interior of said second trenches and a conductive polysilicon gate filling the interior of said second trenches; and

a source contact formed on the top surface of said device and in contact with said base and with said source regions.

2. The device of claim 1, wherein the interiors of each of each of said trenches is filled with a dielectric material.

3. The device of claim 2, wherein said dielectric is silicon dioxide.

4. The device of claim 1, wherein each of said trenches are laterally elongated parallel trenches.

5. The device of claim 4, wherein the interiors of each of said trenches is filled with a dielectric material.

6. The device of claim 1, wherein each of said trenches has a closed cellular topology.

7. The device of claim 2, wherein each of said trenches has a closed cellular topology.

9. The device of claim 1, wherein said dielectric is a highly resistive material which is connected to a source electrode at its top and said drain structure at its bottom and carries an intentional leakage current under blocking conditions to force a uniform electric field distribution along the length of said trench during a blocking condition.

13. The device of claim 2, wherein said dielectric is a semi-insulating polysilicon.

16. The device of claim 2, wherein said dielectric material consists of alternate vertical layers of at least a first and second dielectric of diverse thermal expansion characteristics which, together, match the expansion characteristics of silicon.

17. The device of claim 16, wherein said first and second dielectrics are silicon dioxide and silicon nitride respectively.

18. The device of claim 16, wherein said MOSgated structure comprises a base of the other conductivity type extending across the top of said body, a plurality of spaced source regions of the one conductivity type diffused into said base, a plurality of second trenches in the top of said base and between respective pairs of said trenches, a gate oxide lining the interior of said second trenches and a conductive polysilicon gate filling the interior of said second trenches;

and a source contact formed on the top surface of said device and in contact with said base and with said source regions.

19. The device of claim 16, wherein each of said trenches are laterally elongated parallel trenches.

20. The device of claim 17, wherein each of said trenches are laterally elongated parallel trenches.

21. The device of claim 20, wherein said first and second dielectrics are silicon dioxide and silicon nitride respectively.

22. The device of claim 20, wherein said device contains a plurality of parallel trenches;

each of said trenches being filled by said dielectric filler.

8. A high voltage vertical conduction superjunction semiconductor device comprising:

a body of one conductivity type;

a plurality of spaced vertical trenches formed into the upper surface of said body;

a diffusion of the other conductivity type formed into the interior surface of said plurality of said trenches; and

a MOSgated structure connected to the top of said body and to the top of each of said diffusions;

the thickness and concentration of said diffusion and the width and concentration of said body being matched to insure substantially full depletion of said diffusion and body when blocking voltage is applied to said body; and

wherein the interiors of each of said trenches is filled with a highly resistive material which is connected to a source electrode at its top and said drain structure at its bottom and carries an intentional leakage current under blocking conditions to force a uniform electric field distribution along the length of said trench during a blocking condition.

10. The device of claim 8, wherein each of said trenches are laterally elongated parallel trenches.

11. The device of claim 8, wherein each of said trenches has a closed cellular topology.

14. The device of claim 10, wherein said dielectric is a semi-insulating polysilicon.

15. The device of claim 11, wherein said dielectric is a semi-insulating polysilicon.

12. A high voltage vertical conduction superjunction semiconductor device comprising:

a body of one conductivity type;

a plurality of spaced vertical trenches formed into the upper surface of said body;

a diffusion of the other conductivity type formed into the interior surface of said plurality of said trenches; and

a MOSgated structure connected to the top of said body and to the top of each of said diffusions;

the thickness and concentration of said diffusion and the width and concentration of said body being matched to insure substantially full depletion of said diffusion and body when blocking voltage is applied to said body; and

wherein the interiors of each of said trenches is filled with a semi-insulating polysilicon.