Charge-pump phase-locked loop circuit with charge calibration

• US 6,608,511 B1
• Filed: 07/17/2002
• Issued: 08/19/2003
• Est. Priority Date: 07/17/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Hsu, Wei-Chan
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US10/196,182
• Time in Patent Office: 398 Days
• Field of Search: 327/156, 327/157, 327/536, 327/537, 327/590, 307/110, 363/59, 363/60, 331/1.A, 331/17, 331/25
• US Class Current: 327/157
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

A charge-pump phase-locked loop (PLL) circuit with charge calibration. The PLL keeps the phase of an output clock signal constant in a “locked” condition, and includes a first charge pump, a second charge pump and a charge sensing circuit. The first and the second charge pumps provide a first current and a second current, respectively. According to a first and second net charge delivered from the first and the second currents separately, the charge sensing circuit provides a calibrate voltage signal as feedback to the first charge pump and the second charge pump. Under control of the calibrate voltage signal, the first and the second charge pumps regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of a reference clock signal.

Claims

1. A charge-pump phase-locked loop circuit, comprising:

a first charge pump circuit for providing a first current to cause an output clock signal'"'"'s phase to track a reference clock signal'"'"'s phase; and

a calibration circuit comprising;

a second charge pump circuit for providing a second current to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal; and

a charge sensing circuit for generating a calibrate voltage signal in accordance with a first net charge delivered from the first current and a second net charge delivered from the second current, and for providing the calibrate voltage signal as feedback to the first charge pump and the second charge pump;

wherein the first and the second charge pump circuits, under control of the calibration voltage signal, respectively regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.

2. The charge-pump phase-locked loop as recited in claim 1 wherein the first charge pump comprises a first transistor for fine tuning the first current based on the calibrate voltage signal to eliminate the first net charge.

3. The charge-pump phase-locked loop as recited in claim 2 wherein the first transistor has its gate receiving the calibrate voltage signal.

4. The charge-pump phase-locked loop as recited in claim 1 wherein the second charge pump comprises a second transistor for fine tuning the second current based on the calibrate voltage signal to eliminate the second net charge.

5. The charge-pump phase-locked loop as recited in claim 4 wherein the second transistor has its gate receiving the calibrate voltage signal.

6. The charge-pump phase-locked loop as recited in claim 1 wherein the calibration circuit further comprises a second phase detector for receiving the reference clock signal to simultaneously generate a second pump-up pulse and a second pump-down pulse at a rate of the reference clock signal, and the second charge pump provides the second current in response to the second pump-up and the second pump-down pulses.

7. The charge-pump phase-locked loop as recited in claim 6 further comprising:

a divider for dividing the output clock signal'"'"'s frequency by a given divide ratio;

a voltage-controlled oscillator for generating the output clock signal with variable frequency in accordance with a frequency control voltage signal;

a loop filter for filtering the first current to provide a filtered voltage to the voltage-controlled oscillator as the frequency control voltage signal; and

a first phase detector for detecting phase difference between an output signal of the divider and the reference clock signal to generate a first pump-up pulse and a first pump-down pulse, wherein the first charge pump generates the first current in response to the first pump-up and the first pump-down pulses.

8. The charge-pump phase-locked loop as recited in claim 1 wherein the charge sensing circuit comprises an operational amplifier for sensing the first net charge and the second net charge to generate the calibrate voltage signal.

9. A charge-pump phase-locked loop, comprising:

a first charge pump circuit for providing a first current to cause an output clock signal'"'"'s phase to track a reference clock signal'"'"'s phase;

a first transistor arranged in cascade connection with the first charge pump circuit for fine tuning the first current based on a calibrate voltage signal to eliminate a first net charge delivered from the first current;

a calibration circuit comprising;

a second phase detector, receiving the reference clock signal, for simultaneously generating a second pump-up pulse and a second pump-down pulse at a rate of the reference clock signal;

a second charge pump, responsive to the second pump-up and the second pump-down pulses, for providing a second current to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal;

a second transistor arranged in cascade connection with the second charge pump for fine tuning the second current based on the calibrate voltage signal to eliminate a second net charge delivered from the second current; and

a charge sensing circuit for generating the calibrate voltage signal in accordance with the first net charge and the second net charge, and for providing the calibrate voltage signal as feedback to the first and the second transistors;

wherein the first charge pump with the first transistor and the second charge pump with the second transistor, under control of the calibrate voltage signal, respectively regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.

10. The charge-pump phase-locked loop as recited in claim 9 wherein the first transistor has its gate receiving the calibrate voltage signal.

11. The charge-pump phase-locked loop as recited in claim 9 wherein the second transistor has its gate receiving the calibrate voltage signal.

12. The charge-pump phase-locked loop as recited in claim 9 further comprising:

a divider for dividing the output clock signal'"'"'s frequency by a given divide ratio;

a voltage-controlled oscillator for generating the output clock signal with variable frequency in accordance with a frequency control voltage signal;

a loop filter for filtering the first current to provide a filtered voltage to the voltage-controlled oscillator as the frequency control voltage signal; and

a first phase detector for detecting phase difference between an output signal of the divider and the reference clock signal to generate a first pump-up pulse and a first pump-down pulse, wherein the first charge pump generates the first current in response to the first pump-up and the first pump-down pulses.

13. The charge-pump phase-locked loop as recited in claim 9 wherein the charge sensing circuit comprises an operational amplifier for sensing the first net charge and the second net charge to generate the calibrate voltage signal.

14. A charge-pump phase-locked loop with charge calibration, comprising:

a first charge pump for providing a first current to cause an output clock signal'"'"'s phase to track a reference clock signal'"'"'s phase; and

a calibration circuit comprising;

a second phase detector, receiving the reference clock signal, for simultaneously generating a second pump-up pulse and a second pump-down pulse at a rate of the reference clock signal;

a second charge pump coupled to the second phase detector, for providing a second current in response to the second pump-up and the second pump-down pulses, wherein the second current is used to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal; and

an operational amplifier having a first input terminal coupled to an output terminal of the first charge pump, a second input terminal coupled to an output terminal of the second charge pump, and an output terminal connected to a control node of the first charge pump and a control node of the second charge pump respectively, for providing a calibrate voltage signal as feedback to the first charge pump and the second charge pump;

wherein the first and the second charge pumps, under control of the calibrate voltage signal, respectively regulate a first net charge on the first input terminal of the operational amplifier and a second net charge on the second input terminal of the operational amplifier to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.

15. The charge-pump phase-locked loop as recited in claim 14 wherein the first charge pump comprises a first transistor arranged in cascade connection with the first charge pump, for fine tuning the first current based on the calibrate voltage signal to eliminate the first net charge.

16. The charge-pump phase-locked loop as recited in claim 15 wherein the first transistor has its gate coupled to the control node of the first charge pump to receive the calibrate voltage signal.

17. The charge-pump phase-locked loop as recited in claim 14 wherein the second charge pump comprises a second transistor arranged in cascade connection with the second charge pump, for fine tuning the second current based on the calibrate voltage signal to eliminate the second net charge.

18. The charge-pump phase-locked loop as recited in claim 17 wherein the second transistor has its gate coupled to the control node of the second charge pump to receive the calibrate voltage signal.

19. The charge-pump phase-locked loop as recited in claim 14 further comprising:

a divider for dividing the output clock signal'"'"'s frequency by a given divide ratio;

a voltage-controlled oscillator for generating the output clock signal with variable frequency in accordance with a frequency control voltage signal;

a loop filter coupled to the output terminal of the first charge pump, for filtering the first current to provide a filtered voltage to the voltage-controlled oscillator as the frequency control voltage signal; and

a first phase detector for detecting phase difference between an output signal of the divider and the reference clock signal to generate a first pump-up pulse and a first pump-down pulse, wherein the first charge pump generates the first current in response to the first pump-up and the first pump-down pulses.

20. The charge-pump phase-locked loop as recited in claim 14 wherein the operational amplifier, having the first and the second input terminals and the output terminal, senses the first net charge on its first input terminal and the second net charge on its second input terminal to generate the calibrate voltage signal on its output terminal.