System and method for communicating over a one-wire bus

• US 6,608,571 B1
• Filed: 05/07/2002
• Issued: 08/19/2003
• Est. Priority Date: 05/16/2001
• Status: Expired due to Fees

• Current Assignee: Conexant Incorporated (Synaptics Incorporated)
• Original Assignee: GlobespanVirata, Inc. (Synaptics Incorporated)
• Inventors: Delvaux, Marc
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US10/140,624
• Time in Patent Office: 469 Days
• Field of Search: 341/50, 341/53, 710/100, 710/106, 710/124, 710/305
• US Class Current: 341/53
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A one-wire protocol is described, wherein a one-wire bus has either a wired-AND configuration or a wired-OR configuration. In this protocol, data is encoded using time modulation. In one embodiment, two devices communicate with each other through the one-wire bus. One device is configured to transmit data by driving the one-wire bus high, while the other device is configured to transmit data by driving the one-wire bus low. In a preferred embodiment, transmission of data by each of the two devices is interleaved in such a fashion so that there is a bit-for-bit exchange between one device and the other device. In another embodiment, more than two devices may communicate through the one-wire bus.

Claims

1. A system for transmitting and receiving data over a one-wire bus, comprising:

a one-wire bus having a plurality of devices connected to the one-wire bus, wherein the one-wire bus is configured to be driven high when every device on the one-wire bus is high, wherein the one-wire bus is configured to be driven low when any device on the one-wire bus is low, wherein each of the plurality of devices is configured to count a finite time period, wherein the finite time period is a function of one of the plurality of devices having a slowest clock speed;

a first device configured to encode data using time modulation, wherein a false bit is encoded as a duration of approximately the finite time period, wherein a true bit is encoded as a duration of approximately double the finite time period, wherein absence of data is encoded as a duration of greater than approximately double the finite time period, wherein the first device is further configured to transmit the encoded data by driving the one-wire bus high, wherein the first device is further configured to drive the one-wire bus low for a duration of approximately half of the finite time period upon complete transmission of the encoded data, wherein the first device is further configured to drive the one-wire bus high after driving the one-wire bus low for the duration of approximately half of the finite time period;

a second device configured to encode data using time modulation, wherein a false bit is encoded as a duration of approximately the finite time period, wherein a true bit is encoded as a duration of approximately double the finite time period, wherein absence of data is encoded as a duration of greater than approximately double the finite time period, wherein the second device is further configured to transmit the encoded data by driving the one-wire bus low.

2. A system for transmitting. and receiving data over a one-wire bus, comprising:

a one-wire bus having a plurality of devices connected to the one-wire bus, wherein the one-wire bus is configured to be driven high when every device on the one-wire bus is high, wherein the one-wire bus is configured to be driven low when any device on the one-wire bus is low;

a first device configured to encode data using time modulation, wherein the first device is further configured to transmit the encoded data by driving the one-wire bus high; and

a second device configured to encode data using time modulation, wherein the second device is further configured to transmit the encoded data by driving the one-wire bus low.

3. The system of claim 2, wherein the first device and the second device are configured to interleave data transmission.

4. The system of claim 2, wherein the plurality of devices each have an internal clock period, wherein each of the plurality of devices is configured to count a finite time period using its internal clock period.

5. The system of claim 4, wherein the finite time period is an integer multiple of one of the plurality of devices having a longest internal clock period.

6. The system of claim 4, wherein the first device and the second device are configured to encode a false bit as a duration of approximately the finite time period, wherein the first device and the second device are configured to encode a true bit as a duration of approximately double the finite time period, wherein the first device and the second device are configured to encode absence of data as a duration of greater than approximately double the finite time period.

7. The system of claim 4, wherein the first device and the second device are configured to encode a true bit as a duration of approximately the finite time period, wherein the first device and the second device are configured to encode a false bit as a duration of approximately double the finite time period, wherein the first device and the second device are configured to encode absence of data as a duration of greater than approximately double the finite time period.

8. The system of claim 6, wherein the first device is further configured to drive the one-wire bus low for a duration of approximately half of the finite time period after transmitting data.

9. The system of claim 4, wherein the first device is further configured to transmit data after all of the plurality of devices has counted the finite time period, wherein the data transmitted by the first device is selected from a group consisting of:

a false bit;

a true bit; and

absence of data.

10. The system of claim 9, wherein the second device is further configured to receive the data transmitted by the first device, wherein the second device is further configured to transmit data in response to the data received from the first device, wherein the data transmitted by the second device is selected from a group consisting of:

a false bit;

a true bit; and

absence of data.

11. The system of claim 10, wherein the first device is further configured to receive the data transmitted by the second device, wherein the first device is further configured to transmit data in response to the data received from the second device.

12. A system for transmitting and receiving data over a one-wire bus, comprising:

a one-wire bus having a plurality of devices connected to the one-wire bus, wherein the one-wire bus is configured to be driven low when every device on the one-wire bus is low, wherein the one-wire bus is configured to be driven high when any device on the one-wire bus is high;

a first device configured to encode data using time modulation, wherein the first device is further configured to transmit the encoded data by driving the one-wire bus high; and

a second device configured to encode data using time modulation, wherein the second device is further configured to transmit the encoded data by driving the one-wire bus low.

13. A method for transmitting and receiving data over a one-wire bus, comprising the steps of:

transmitting time-modulated data by driving the one-wire bus high, wherein the one-wire bus is driven high when every device on the one-wire bus is high; and

transmitting time-modulated data by driving the one-wire bus low, wherein the one-wire bus is driven low when any device on the one-wire bus is low.

14. The method of claim 13, further comprising the step of interleaving the step of transmitting time-modulated data by driving the one-wire bus high and the step of transmitting data by driving the one-wire bus low.

15. The method of claim 13, further comprising the step of synchronizing every device on the one-wire bus.

16. The method of claim 15, wherein the step of synchronizing every device on the one-wire bus comprises the step of determining a finite time period.

17. The method of claim 16, wherein the step of determining a finite time period comprises the steps of:

producing a low output;

counting a predetermined number of clock periods after producing the low output;

producing a high output in response to the counting of the predetermined number of clock periods;

polling a one-wire bus after producing the high output to determine when the one-wire bus goes high;

counting a number of clock periods between the production of the low output and the determination of when the one-wire bus goes high.

18. The method of claim 16, wherein the step of transmitting time-modulated data by driving the one-wire bus high is responsive to the step of synchronizing every device on the one-wire bus.

19. The method of claim 16, wherein the step of transmitting time-modulated data by driving the one-wire bus low is responsive to the step of transmitting time-modulated data by driving the one-wire bus high.

20. The method of claim 16, wherein the step of transmitting time-modulated data by driving the one-wire bus high is responsive to the step of transmitting time-modulated data by driving the one-wire bus low.

21. The method of claim 16, wherein the step of transmitting time-modulated data by driving the one-wire bus high further comprises the step of determining data content, wherein the data content is selected from a group consisting of:

a false bit;

a true bit; and

absence of data.

22. The method of claim 21, further comprising the steps of:

defining the false bit as a duration of time equal to approximately the finite time period;

defining the true bit as a duration of time equal to approximately double the finite time period; and

defining absence of data as a duration of time greater than approximately double the finite time period.

23. The method of claim 16, further comprising the step of driving the one-wire bus low in response to the step of transmitting time-modulated data by driving the one-wire bus high.

24. The method of claim 16, further comprising the step of receiving data in response to the step of transmitting time-modulated data by driving the one-wire bus high.

25. The method of claim 16, wherein the step of transmitting time-modulated data by driving the one-wire bus low further comprises the step of determining data content, wherein the data content is selected from a group consisting of:

a false bit;

a true bit; and

absence of data.

26. The method of claim 25, further comprising the steps of:

defining the false bit as a duration of time equal to approximately the finite time period;

defining the true bit as a duration of time equal to approximately double the finite time period; and

defining absence of data as a duration of time greater than approximately double the finite time period.

27. The method of claim 16, further comprising the step of driving the one-wire bus high in response to the step of transmitting time-modulated data by driving the one-wire bus low.

28. The method of claim 16, further comprising the step of receiving data in response to the step of transmitting time-modulated data by driving the one-wire bus low.

29. A system for transmitting and receiving data over a one-wire bus, comprising:

a one-wire bus having a plurality of devices connected to the one-wire bus, wherein the one-wire bus is configured to be driven high when every device on the one-wire bus is high, wherein the one-wire bus is configured to be driven low when any device on the one-wire bus is low;

means for encoding data using time modulation;

means for transmitting the encoded data by driving the one-wire bus high; and

means for transmitting the encoded data by driving the one-wire bus low.

30. A system for transmitting and receiving data over a one-wire bus, comprising:

a one-wire bus having a plurality of devices connected to the one-wire bus, wherein the one-wire bus is configured to be driven low when every device on the one-wire bus is low, wherein the one-wire bus is configured to be driven high when any device on the one-wire bus is high;

means for encoding data using time modulation;

means for transmitting the encoded data by driving the one-wire bus high; and

means for transmitting the encoded data by driving the one-wire bus low.