Method for making a printed wiring board

• US 6,608,757 B1
• Filed: 03/18/2002
• Issued: 08/19/2003
• Est. Priority Date: 03/18/2002
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lauffer, John M., Markovich, Voya R., Miller, Thomas R., Bhatt, Ashwinkumar C., Desai, Subahu D., Bhatt, Anilkumar C.
• Primary Examiner(s): Graybill, David E.
• Assistant Examiner(s): MITCHELL, JAMES M
• Application Number:
  US10/101,277
• Time in Patent Office: 519 Days
• Field of Search: 174/255, 174/264, 174/261, 174/262, 298/42, 361/748, 257/686
• US Class Current: 361/748
• CPC Class Codes: H05K 1/056 the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 2203/143 Treating holes before another process, e.g. coating holes before coating the substrate
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/0082 characterised by the exposure method of radiation-sensitive masks
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores

Abstract

Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Claims

1. A process for making a printed wiring board (PWB) structure comprising the steps of

providing an electrically conductive power plane having a first plane side and a second plane side and one or more via holes extending through said electrically conductive power plane from said first plane side to said second plane side;

applying a photo-imageable dielectric (PID) material to said first plane side of said electrically conductive power plane substantially filling said one or more via holes forming filled via holes;

exposing said second plane side of said electrically conductive power plane to light energy to substantially cure all of said PID material in said one or more via holes forming cured PID material;

applying a developer to said electrically conductive power plane after said exposing step, said developer removing substantially all of said PID material that remains uncured after said exposing step; and

laminating a first signal plane assembly to said first plane side of said electrically conductive power plane, said first signal plane assembly comprising a first electrically conductive signal plane and a first dielectric material layer having a uniform first thickness, wherein portions of said first dielectric material layer flow to fill areas of said one or more via holes not filled by said cured PID material.

2. The process of claim 1, wherein said PID material comprises IBM ASM material or Morton Electronic Materials Dynavia 2000 material.

3. The process of claim 1 further comprising the step of:

laminating a second signal plane assembly to said second plane side of said electrically conductive power plane, said second signal plane assembly comprising a second electrically conductive signal plane and a second dielectric material layer having a uniform second thickness.

4. The process of claim 3 further comprising the steps of:

forming an insulated via hole substantially in a center of each of said filled via holes by removing a cylindrical portion of said cured PID material;

applying conductive material in each said insulated via hole to electrically connect said first electrically conductive signal plane to said second electrically conductive signal plane; and

forming circuit lines on said first and second electrically conductive signal planes.

5. The process of claim 3, wherein said uniform first and second thicknesses are of substantially equal value.

6. The process of claim 3, wherein portions of said second dielectric material layer flow to fill areas of said one or more via holes not filled by said cured PID material.

7. A process for making a printed wiring board (PWB) structure comprising the steps of:

providing an electrically conductive power plane having a first plane side and a second plane side and one or more via holes formed and extending through said electrically conductive power plane from said first plane side to said second plane side;

applying a photo-imageable dielectric (PID) material to said first and second plane sides of said electrically conductive power plane substantially filling said one or more via holes forming filled via holes;

placing a photo-mask on said first plane side of said electrically conductive power plane,

exposing said photo-mask on said first plane side of said electrically conductive power plane to light energy to substantially cure all of said PID material in said filled via holes,

applying a developer to said electrically conductive power plane after said exposing step, said developer removing substantially all of said PID material that remains uncured after said exposing step; and

laminating a first signal plane assembly to said first plane side of said electrically conductive power plane, said first signal plane assembly comprising a first electrically conductive signal plane and a first dielectric material layer having a uniform first thickness, wherein portions of said first dielectric material layer flow to fill areas of said one or more via holes not filled by said cured PID material.

8. The process of claim 7, wherein said PID material comprises IBM ASM material or Morton Electronic Materials Dynavia 2000 material.

9. The process of claim 7 further comprising the step of:

laminating a second signal plane assembly to said second plane side of said electrically conductive power plane, said second signal plane assembly comprising a second electrically conductive signal plane and a second dielectric material layer having a uniform second thickness.

10. The process of claim 9 further comprising the steps of:

forming an insulated via hole substantially in a center of each of said filled via holes by removing a cylindrical portion of said cured PID material;

applying conductive material in each said insulated via hole to electrically connect said first electrically conductive signal plane to said second electrically conductive signal plane; and

forming circuit lines on said first and second electrically conductive signal planes.

11. The process of claim 9, wherein said uniform first and second thicknesses are of substantially equal value.

12. The process of claim 9, wherein portions of said second dielectric material layer flow to fill areas of said one or more via holes not filled by said cured PID material.