Hysteresis reduced sense amplifier and method of operation

• US 6,608,789 B2
• Filed: 12/21/2001
• Issued: 08/19/2003
• Est. Priority Date: 12/21/2001
• Status: Expired due to Term

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hoekstra, George P., Pelley, Perry H., Sullivan, Steven C.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US10/027,547
• Publication Number:
  US 20030117873A1
• Time in Patent Office: 606 Days
• Field of Search: 365/205, 365/207, 365/203, 327/55, 327/52, 327/51
• US Class Current: 365/205
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier'"'"'s outputs.

Claims

1. Sense amplifier circuitry, comprising:

a plurality of body isolated transistors coupled to provide differential sensing; and

control circuitry having a first terminal coupled to a first body portion of one of the plurality of body isolated transistors, a second terminal coupled to a second body portion of another one of the plurality of body isolated transistors, and a third terminal for receiving a body control signal, the control circuitry selectively coupling the first and second body portions together to charge share by distributing mismatched charges in the first and second body portions in response to the body control signal, the control circuitry thereby substantially equalizing body voltage of the first and second body portions to a voltage between a differential voltage in the first and second body portions.

2. The sense amplifier circuitry of claim 1, wherein the control circuitry comprises a transistor, the transistor having a first current electrode coupled to the first terminal, a second current electrode coupled to the second terminal, and a control electrode coupled to the third terminal.

3. The sense amplifier circuitry of claim 1, wherein the control circuitry couples the first body portion and the second body portion.

4. Sense amplifier circuitry, comprising:

a first input/output node for receiving a first input signal;

a first isolated body transistor coupled to the first input/output node;

a second input/output node for receiving a second input signal;

a second isolated body transistor cross-coupled to the first isolated body transistor and coupled to the second input/output node, the first isolated body transistor and the second isolated body transistor coupled to provide an amplified output signal at the first input/output node and the second input/output node; and

a body shorting device coupled between the first isolated body transistor and the second isolated body transistor, the body shorting device being responsive to a body control signal, wherein the body shorting device selectively electrically short circuits a body portion of the first isolated body transistor to a body portion of the second isolated body transistor to substantially equalize body voltage of the first isolated body transistor and the second isolated body transistor to a voltage between a differential voltage in the body portion of the first isolated body transistor and the second isolated body transistor.

5. The sense amplifier circuitry of claim 4, wherein when the body control signal is asserted, the body shorting device electrically short circuits the body portion of the first isolated body transistor to the body portion of the second isolated body transistor.

6. The sense amplifier circuitry of claim 5, wherein the body control signal is asserted in response to the first and second input/output nodes being charged to a predetermined charge level.

7. The sense amplifier circuitry of claim 6, wherein the predetermined charge level corresponds to a precharge voltage potential.

8. The sense amplifier circuitry of claim 4, wherein the body shorting device comprises a transistor selected from a group consisting of an N-channel transistor and a P-channel transistor.

9. The sense amplifier circuitry of claim 8, wherein the transistor comprises:

a first current electrode connected to the body portion of the first isolated body transistor;

a second current electrode connected to the body portion of the second isolated body transistor; and

a control electrode for receiving the body control signal.

10. The sense amplifier circuitry of claim 4, wherein each of the first isolated body transistor and the second isolated body transistor comprises an N-channel transistor or a P-channel transistor.

11. Sense amplifier circuitry, comprising:

a cross-coupled differential sensing pair of isolated body transistors, each of the pair of isolated body transistors having a body portion to provide body portions susceptible to mismatched charges; and

control circuitry for distributing the mismatched charges of the body portions between each of the pair of isolated body transistors by substantially equalizing a first body voltage and a second body voltage to a voltage between a differential of the first body voltage and the second body voltage.

12. The sense amplifier circuitry of claim 11, wherein the control circuitry further comprises a single transistor that selectively directly connects each body portion of the pair of isolated body transistors.

13. The sense amplifier circuitry of claim 11, wherein the control circuitry distributes the mismatched charges within a predetermined amount of time.

14. The sense amplifier circuitry of claim 13, wherein the predetermined amount of time occurs between read accesses to the sense amplifier circuitry.

15. The sense amplifier circuitry of claim 11, wherein the control circuitry comprises at least one of an N-channel transistor and a P-channel transistor coupled between the body portions of the isolated body transistors in the pair of isolated body transistors.

16. A method for operating a sense amplifier having a first input/output node, a second input/output node, a first isolated body transistor cross coupled to a second isolated body transistor to provide differential sensing at the first and second input/output nodes, the first isolated body transistor having a first body voltage and the second isolated body transistor having a second body voltage, the method comprising:

sensing a read access to the sense amplifier;

asserting a precharge signal;

in response to asserting the precharge signal, precharging the first and second input/output nodes to a predetermined voltage level, wherein the first body voltage reaches a first voltage level and the second voltage reaches a second voltage level, different from the first voltage level;

asserting a body control signal after asserting the precharge signal; and

in response to asserting the body control signal, connecting a body portion of the first isolated body transistor to a body portion of the second isolated body transistor to equalize the first body voltage and the second body voltage to a voltage between the first body voltage and the second body voltage.

17. The method of claim 16, further comprising:

equalizing the first body voltage and the second body voltage by enabling a single transistor to connect the body portion of the first isolated body transistor to the body portion of the second isolated body transistor response.

18. The method of claim 16, wherein the body control signal is asserted at a predetermined amount of time after asserting the precharge signal.

19. The method of claim 18, wherein the body control signal is asserted after precharging the first and second input/output nodes to the predetermined voltage level.

20. The method of claim 16, further comprising negating the body control signal prior to sensing the read access.