Semiconductor device including memory with reduced current consumption

• US 6,608,795 B2
• Filed: 10/23/2002
• Issued: 08/19/2003
• Est. Priority Date: 09/01/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arimoto, Kazutami, Shimano, Hiroki
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/277,879
• Publication Number:
  US 20030039160A1
• Time in Patent Office: 300 Days
• Field of Search: 365/230.03, 365/230.06, 365/233, 365/230.01
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

When a row active command ACT_CMD is externally input, an internal clock control circuit activates a signal int.CKE, so that an external clock signal ext.CLK is responsively supplied to an internal memory array as signal int.CLK. Thus, clock control is meticulously conducted, whereby a system LSI with reduced current consumption in the memory array can be realized.

Claims

1. A semiconductor device, comprising:

a plurality of memory banks capable of designating a different row address, each of said memory banks including a plurality of memory cells arranged in rows and columns, and conducting data transmission and reception in synchronization with a clock signal; and

a plurality of row address processing circuits provided corresponding to the respective memory banks, said row address processing circuits being responsive to said clock signal for accepting and holding a row address signal applied in order to specify a row of said memory cells, wherein

each of said row address processing circuits includes

a flip-flop circuit for accepting said row address signal in response to said clock signal, and

a clock supply circuit for discontinuing supply of said clock signal to said flip-flop circuit after the corresponding memory bank is selected and said row address signal is accepted in said flip-flop circuit.