Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages

• US 6,609,209 B1
• Filed: 12/29/1999
• Issued: 08/19/2003
• Est. Priority Date: 12/29/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Medapati, Suri B., Makineni, Sivakumar, Sharma, Vinod, Tiwari, Vivek
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/474,461
• Time in Patent Office: 1,329 Days
• Field of Search: 713/300, 713/320, 713/322, 713/600, 713/601
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

Claims

1. A processor comprising:

a pipeline having first and second stages;

a shift register having first and second latches; and

an interface circuit to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

2. The processor of claim 1, wherein the clock signal line is coupled to the shift register to provide the clock signal to the shift register to control shifting of bits from the first latch to the second latch.

3. The processor of claim 2, wherein the clock signal, when provided to the first and second stages, clocks forwarding of data from the first stage to the second stage.

4. The processor of claim 3, wherein the first and second bits indicate if data in the first and second stages, respectively, is valid.

5. The processor of claim 4, wherein the interface circuit includes a plurality of logic gates to provide the clock signal to the first stage if the first bit indicates that data in the first stage is valid, and to provide the clock signal to the second stage if the second bit indicates that data in the second stage is valid.

6. The processor of claim 4, wherein the interface circuit includes a plurality of logic gates to provide the clock signal to both the first and second stages if either the first or second bit indicates that data in either the first or second stage is valid.

7. The processor of claim 1, wherein the interface circuit includes a plurality of logic gates to provide the clock signal to the first stage if data in the first stage is valid, and to provide the clock signal to the second stage if data in the second stage is valid, the first and second bits to indicate, at least in part, if data in the first and second stages, respectively, is valid.

8. The processor of claim 7, wherein the pipeline is a replay pipeline.

9. The processor of claim 7, wherein the pipeline is a non-replay pipeline.

10. The processor of claim 1, wherein the interface circuit includes a plurality of logic gates to provide the clock signal to the first and second stages if data in either the first or second stage is valid, the first and second bits to indicate, at least in part, if data in the first and second stages, respectively, is valid.

11. The processor of claim 1, further comprising an initialization array to store a first set of initial values for the first and second bits to be stored in the first and second latches, respectively, upon a replay of the pipeline.

12. The processor of claim 11, wherein the initialization array is to further store a second set of initial values for the first and second bits to be stored in the first and second latches, respectively, upon a replay of the pipeline, selection between the first and second sets of initial values to be determined, at least in part, by a replay type.

13. The processor of claim 11, wherein the interface circuit includes a plurality of logic gates to provide the clock signal to the first stage if data in the first stage is valid, and to provide the clock signal to the second stage if data in the second stage is valid, the first and second bits to indicate, at least in part, if data in the first and second stages, respectively, is valid.

14. A computer system comprising:

a processor;

a system clock to provide a clock signal to the processor;

a power supply to supply power to the processor;

a pipeline of the processor having a plurality of stages;

a shift register having a plurality of latches, each latch being associated with one of the stages; and

an interface circuit coupled to the pipeline and the shift register to provide the clock signal to each stage based, at least in part, on a bit to be stored in each stage'"'"'s associated latch and to reduce the power supplied by the power supply by preventing the clock signal from being provided to each stage based, at least in part, on a bit to be stored in each stage'"'"'s associated latch.

15. The system of claim 14, wherein each bit to be stored in each stage'"'"'s associated latch indicates, at least in part, if data in an associated stage is valid.

16. The system of claim 15, further comprising a clock signal line coupled to the shift register to provide the clock signal to the shift register to control shifting of bits between the latches.

17. The system of claim 15, wherein the interface circuit includes a plurality of logic gates to prevent the clock signal from being provided to the plurality of stages if data in all of the plurality stages is invalid.

18. The system of claim 16, wherein the interface circuit includes a plurality of logic gates to prevent the clock signal from being provided to a stage of the plurality of stages if data in the stage is invalid.

19. The system of claim 18, further comprising an initialization array to store a first set of initial values for each bit to be stored in each latch upon a replay of the pipeline.

20. The system of claim 19, wherein the initialization array is to further store a second set of initial values for each bit to be stored in each latch upon a replay of the pipeline, selection between the first and second sets of initial values to be determined, at least in part, by a replay type.

21. A method of operating a processor comprising:

storing a bit in each of a plurality of latches of a shift register, each latch having an associated pipeline stage of a pipeline, each bit of each latch having associated data in the pipeline stage and indicating if the associated data is valid; and

providing a clock signal to a pipeline stage if data in the stage is valid, as determined, at least in part, by its associated bit.

22. The method of claim 21, further comprising flushing at least a portion of the pipeline, and initializing the latches of the shift register.

23. The method of claim 21, further comprising replaying at least a portion of the pipeline, and initializing the latches of the shift register.

24. The method of claim 23, wherein initializing the latches includes loading a set of initial values from an initialization array into the latches.

25. The method of claim 21, further comprising shifting each bit of each latch in tandem with forwarding the associated data.