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Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor

  • US 6,610,566 B2
  • Filed: 12/05/2000
  • Issued: 08/26/2003
  • Est. Priority Date: 10/06/1997
  • Status: Expired due to Fees
First Claim
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1. A method of forming a memory cell comprising:

  • forming an access transistor, comprising;

    forming a pillar of semiconductor material that extends outwardly from a substrate;

    forming a first source/drain region from a portion of the pillar of semiconductor material;

    forming a body region from a portion of the pillar of semiconductor material, the body region being coupled to the first source/drain region;

    forming a second source/drain region from a portion of the pillar of semiconductor material, the second source/drain region being coupled to the body region;

    forming a trench capacitor, wherein a first plate of the trench capacitor is formed from a portion of the pillar of semiconducting material adjacent to the second source/drain region.

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