Method of forming PID protection diode for SOI wafer

• US 6,611,024 B2
• Filed: 09/06/2001
• Issued: 08/26/2003
• Est. Priority Date: 07/12/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Ang, Ting Cheong, Song, Jun, Loong, Sang Yee, Quek, Shyue Fong
• Primary Examiner(s): Meier, Stephen D.
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US09/946,981
• Publication Number:
  US 20020022328A1
• Time in Patent Office: 719 Days
• Field of Search: 257/350, 257/357, 257/355, 257/356, 438/237, 438/406, 438/407, 438/152
• US Class Current: 257/350
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Claims

1. An integrated semiconductor microelectronics circuit formed on an SOI substrate and protected by a heat-dissipating PID diode, comprising:

an SOI substrate, said substrate comprising upper and lower layers of silicon, with an insulating layer formed therebetween;

a plurality of nMOS and pMOS type transistor devices with silicided source/drain and gate electrode contacts, formed in the upper silicon layer of said SOI substrate;

a PID protective diode formed as a junction in the lower silicon layer of said SOI substrate;

an ILD formed over said circuit, through which pass conducting contacts to the transistor devices and PID protective diode.

a heat and charge dissipating metal layer formed over the ILD layer, said metal layer being in electrical contact with the contact from the PID diode, but not being in electrical contact with the contacts of said transistors.

2. The circuit of claim 1, wherein the SOI substrate has been formed by the SIMOX method or by a method of wafer bonding.

3. The circuit of claim 1, wherein the upper and lower silicon layers of the SOI substrate are doped with a low density of p-type ions.

4. The circuit of claim 3, wherein the PID diode is an np type diode having a low density of n-type ions implanted in the lower p-type silicon layer of the SOI substrate, said ions being implanted to a density of between 5E13 and 1E15 ions per cubic centimeter.

5. The circuit of claim 1, wherein the contacts through the ILD to the PID diode and silicided regions of the MOS devices are formed of tungsten.

6. The circuit of claim 1, wherein the metal layer covering the ILD is shaped such that it optimally collects excess charges and dissipates heat generated by subsequent fabrication processes, such shapes being chosen from the group consisting of perimeter pieces, fingers and antenna shaped projections, and such shapes being formed so as to maintain a certain minimum distance from any nearby conductive contacts to the circuitry below.

7. The circuit of claim 1, wherein the spacing between the metal layer and any nearby conductive contacts is at least the width of those conductive contacts.

8. The circuit of claim 1, further including a plurality of levels of microelectronic circuitry, said levels being covered by conducting layers which are connected, through vias, to said PID protective diode.