Wafer level stackable semiconductor package
First Claim
1. A semiconductor package comprising:
- a semiconductor die comprising a plurality of integrated circuits and having a first side, an opposing second side, and a peripheral edge;
a plurality of first pads on the first side in electrical communication with the integrated circuits;
a plurality of conductive grooves in the peripheral edge in electrical communication with the first pads;
a plurality of second pads on the second side in electrical communication with the conductive grooves; and
a plurality of first conductors on the first side in electrical communication with the first pads and the conductive grooves and a plurality of second conductors on the second side in electrical communication with the second pads and the conductive grooves;
the first pads and the second pads having matching patterns and configured for bonding to a second package substantially identical to the package.
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Accused Products
Abstract
A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is if performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.
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Citations
39 Claims
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1. A semiconductor package comprising:
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a semiconductor die comprising a plurality of integrated circuits and having a first side, an opposing second side, and a peripheral edge;
a plurality of first pads on the first side in electrical communication with the integrated circuits;
a plurality of conductive grooves in the peripheral edge in electrical communication with the first pads;
a plurality of second pads on the second side in electrical communication with the conductive grooves; and
a plurality of first conductors on the first side in electrical communication with the first pads and the conductive grooves and a plurality of second conductors on the second side in electrical communication with the second pads and the conductive grooves;
the first pads and the second pads having matching patterns and configured for bonding to a second package substantially identical to the package. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor package comprising:
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a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side, and opposing peripheral edges;
a plurality of circuit side conductors on the circuit side in electrical communication with the integrated circuits, and circuit side stacking pads on the circuit side in electrical communication with the circuit side conductors;
a plurality of collinear pairs of conductive grooves in the opposing peripheral edges in electrical communication with the circuit side conductors;
a plurality of back side conductors on the back side in electrical communication with the conductive grooves, and back side stacking pads on the back side in electrical communication with the back side conductors; and
a plurality of contacts on the circuit side stacking pads or on the back side stacking pads. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor package comprising:
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a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side and a peripheral edge;
a plurality of stacking contacts on the circuit side in a selected pattern in electrical communication with the integrated circuits;
a plurality of stacking pads on the back side in the selected pattern in electrical communication with the stacking contacts;
a plurality of conductive grooves in the peripheral edge configured as interlevel conductors between the stacking contacts and the stacking pads; and
a plurality of circuit side conductors on the circuit side in electrical communication with the stacking contacts and the conductive grooves and a plurality of back side conductors on the back side in electrical communication with the stacking pads and the conductive grooves;
the stacking contacts configured for bonding to a second package, the stacking pads configured for bonding to a third package. - View Dependent Claims (12, 13, 14)
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15. A semiconductor package comprising:
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a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side and a peripheral edge;
a plurality of stacking pads on the circuit side in a selected pattern in electrical communication with the integrated circuits;
a plurality of stacking contacts on the back side in the selected pattern in electrical communication with the stacking pads;
a plurality of conductive grooves in the peripheral edge configured as interlevel conductors between the stacking pads and the stacking contacts; and
a plurality of circuit side conductors on the circuit side in electrical communication with the stacking pads and the conductive grooves and a plurality of back side conductors on the back side in electrical communication with the stacking contacts and the conductive grooves;
the stacking pads configured for bonding to a second package, the stacking contacts configured for bonding to a third package. - View Dependent Claims (16, 17, 18)
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19. A semiconductor package comprising:
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a semiconductor die comprising a plurality of integrated circuits and having a first side, an opposing second side, and opposing peripheral edges;
a plurality of first conductors on the first side in electrical communication with the integrated circuits;
a plurality of pairs of collinear conductive grooves in the peripheral edges in electrical communication with the first conductors; and
a plurality of second conductors on the second side in electrical communication with the conductive grooves;
a plurality of stacking contacts on the first side in electrical communication with the first conductors and having a selected pattern; and
a plurality of stacking pads on the second side in electrical communication with the second conductors and having the selected pattern. - View Dependent Claims (20, 21, 22)
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23. A semiconductor package comprising:
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a semiconductor die comprising a plurality of integrated circuits and having a circuit side, an opposing back side, and a peripheral edge;
a plurality of circuit side conductors on the circuit side in electrical communication with the integrated circuits;
a plurality of conductive grooves in the peripheral edge in electrical communication with the circuit side conductors;
a plurality of back side conductors on the back side in electrical communication with the conductive grooves;
a plurality of stacking pads on the circuit side in electrical communication with the circuit side conductors and having a selected pattern; and
a plurality of stacking contacts on the back side in electrical communication with the back side conductors and having the selected pattern. - View Dependent Claims (24, 25, 26)
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27. A stacked semiconductor assembly comprising:
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a first semiconductor package comprising a plurality of integrated circuits and having a first side, an opposing second side, and a peripheral edge;
a plurality of first pads on the first side in electrical communication with the integrated circuits;
a plurality of conductive grooves in the peripheral edge in electrical communication with the first pads;
a plurality of second pads on the second side in electrical communication with the conductive grooves;
a plurality of first conductors on the first side in electrical communication with the first pads and the conductive grooves and a plurality of second conductors on the second side in electrical communication with the second pads and the conductive grooves; and
a second package substantially identical to the package, stacked on the package and bonded to the first pads or to the second pads. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35)
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36. A stacked semiconductor assembly comprising:
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a first package and a second package each package comprising;
a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side and a peripheral edge;
a plurality of stacking pads on the first side in a selected pattern in electrical communication with the integrated circuits;
a plurality of stacking contacts on the second side in the selected pattern in electrical communication with the stacking pads;
a plurality of conductive grooves in the peripheral edge configured as interlevel conductors between the stacking pads and the stacking contacts; and
a plurality of circuit side conductors on the circuit side in electrical communication with the stacking pads and the conductive grooves and a plurality of back side conductors on the back side in electrical communication with the stacking contacts and the conductive grooves;
the first package stacked to the second package with the stacking contacts on the first package bonded to the stacking pads on the second package. - View Dependent Claims (37, 38, 39)
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Specification