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Wafer level stackable semiconductor package

  • US 6,611,052 B2
  • Filed: 11/16/2001
  • Issued: 08/26/2003
  • Est. Priority Date: 11/16/2001
  • Status: Expired due to Term
First Claim
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1. A semiconductor package comprising:

  • a semiconductor die comprising a plurality of integrated circuits and having a first side, an opposing second side, and a peripheral edge;

    a plurality of first pads on the first side in electrical communication with the integrated circuits;

    a plurality of conductive grooves in the peripheral edge in electrical communication with the first pads;

    a plurality of second pads on the second side in electrical communication with the conductive grooves; and

    a plurality of first conductors on the first side in electrical communication with the first pads and the conductive grooves and a plurality of second conductors on the second side in electrical communication with the second pads and the conductive grooves;

    the first pads and the second pads having matching patterns and configured for bonding to a second package substantially identical to the package.

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