Wafer level stackable semiconductor package

• US 6,611,052 B2
• Filed: 11/16/2001
• Issued: 08/26/2003
• Est. Priority Date: 11/16/2001
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Loo, Neo Yong, Kwang, Chua Swee, Waf, Low Siu, Yu, Chan Min
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T.
• Application Number:
  US10/042,560
• Publication Number:
  US 20030094683A1
• Time in Patent Office: 648 Days
• Field of Search: 257/686, 257/780, 257/690, 257/685, 257/737, 361/803, 439/71, 365/51
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers

Abstract

A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is if performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.

Claims

1. A semiconductor package comprising:

a semiconductor die comprising a plurality of integrated circuits and having a first side, an opposing second side, and a peripheral edge;

a plurality of first pads on the first side in electrical communication with the integrated circuits;

a plurality of conductive grooves in the peripheral edge in electrical communication with the first pads;

a plurality of second pads on the second side in electrical communication with the conductive grooves; and

a plurality of first conductors on the first side in electrical communication with the first pads and the conductive grooves and a plurality of second conductors on the second side in electrical communication with the second pads and the conductive grooves;

the first pads and the second pads having matching patterns and configured for bonding to a second package substantially identical to the package.

2. The package of claim 1 further comprising bumps or balls on the first pads.

3. The package of claim 1 further comprising bumps or balls on the second pads.

4. The package of claim 1 wherein the conductive grooves comprise arcuate or semicircular openings and a conductive material in the openings.

5. The package of claim 1 further comprising a plurality of collinear pairs of conductive grooves on opposing edges of the die.

6. A semiconductor package comprising:

a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side, and opposing peripheral edges;

a plurality of circuit side conductors on the circuit side in electrical communication with the integrated circuits, and circuit side stacking pads on the circuit side in electrical communication with the circuit side conductors;

a plurality of collinear pairs of conductive grooves in the opposing peripheral edges in electrical communication with the circuit side conductors;

a plurality of back side conductors on the back side in electrical communication with the conductive grooves, and back side stacking pads on the back side in electrical communication with the back side conductors; and

a plurality of contacts on the circuit side stacking pads or on the back side stacking pads.

7. The package of claim 6 wherein the contacts are on the circuit side stacking pads and comprise ball or bumps configured for bonding to a second semiconductor package substantially identical to the package.

8. The package of claim 6 further comprising a plurality of external contacts on the back side stacking pads in electrical communication with the back side conductors.

9. The package of claim 6 wherein the conductive grooves comprise arcuate or semicircular openings at least partially covered with conductive layers.

10. The package of claim 6 wherein the contacts comprise external contacts configured to electrically connect the package to a supporting substrate.

11. A semiconductor package comprising:

a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side and a peripheral edge;

a plurality of stacking contacts on the circuit side in a selected pattern in electrical communication with the integrated circuits;

a plurality of stacking pads on the back side in the selected pattern in electrical communication with the stacking contacts;

a plurality of conductive grooves in the peripheral edge configured as interlevel conductors between the stacking contacts and the stacking pads; and

a plurality of circuit side conductors on the circuit side in electrical communication with the stacking contacts and the conductive grooves and a plurality of back side conductors on the back side in electrical communication with the stacking pads and the conductive grooves;

the stacking contacts configured for bonding to a second package, the stacking pads configured for bonding to a third package.

12. The package of claim 11 wherein each stacking contact comprises a bump or a ball.

13. The package of claim 11 wherein each stacking contact comprises a non-oxidizing metal layer.

14. The package of claim 11 further comprising a plurality of external contacts on the back side in electrical communication with the stacking pads.

15. A semiconductor package comprising:

a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side and a peripheral edge;

a plurality of stacking pads on the circuit side in a selected pattern in electrical communication with the integrated circuits;

a plurality of stacking contacts on the back side in the selected pattern in electrical communication with the stacking pads;

a plurality of conductive grooves in the peripheral edge configured as interlevel conductors between the stacking pads and the stacking contacts; and

a plurality of circuit side conductors on the circuit side in electrical communication with the stacking pads and the conductive grooves and a plurality of back side conductors on the back side in electrical communication with the stacking contacts and the conductive grooves;

the stacking pads configured for bonding to a second package, the stacking contacts configured for bonding to a third package.

16. The package of claim 15 wherein each stacking contact comprises a bump or a ball.

17. The package of claim 15 wherein each stacking contact comprises a bump or a ball.

18. The package of claim 15 further comprising a plurality of external contacts on the back side in electrical communication with the stacking contacts.

19. A semiconductor package comprising:

a semiconductor die comprising a plurality of integrated circuits and having a first side, an opposing second side, and opposing peripheral edges;

a plurality of first conductors on the first side in electrical communication with the integrated circuits;

a plurality of pairs of collinear conductive grooves in the peripheral edges in electrical communication with the first conductors; and

a plurality of second conductors on the second side in electrical communication with the conductive grooves;

a plurality of stacking contacts on the first side in electrical communication with the first conductors and having a selected pattern; and

a plurality of stacking pads on the second side in electrical communication with the second conductors and having the selected pattern.

20. The package of claim 19 wherein the stacking contacts are configured for bonding to a second package substantially identical to the package.

21. The package of claim 19 further comprising a plurality of external contacts on the second side on the stacking contacts.

22. The package of claim 19 wherein the stacking contacts comprise external contacts for the package.

23. A semiconductor package comprising:

a semiconductor die comprising a plurality of integrated circuits and having a circuit side, an opposing back side, and a peripheral edge;

a plurality of circuit side conductors on the circuit side in electrical communication with the integrated circuits;

a plurality of conductive grooves in the peripheral edge in electrical communication with the circuit side conductors;

a plurality of back side conductors on the back side in electrical communication with the conductive grooves;

a plurality of stacking pads on the circuit side in electrical communication with the circuit side conductors and having a selected pattern; and

a plurality of stacking contacts on the back side in electrical communication with the back side conductors and having the selected pattern.

24. The package of claim 23 wherein the stacking contacts are configured for bonding to a second package substantially identical to the package.

25. The package of claim 23 wherein the stacking contacts comprise external contacts for the package.

26. The package of claim 23 wherein the conductive grooves are configured as collinear pairs on opposing edges of the die.

27. A stacked semiconductor assembly comprising:

a first semiconductor package comprising a plurality of integrated circuits and having a first side, an opposing second side, and a peripheral edge;

a plurality of first pads on the first side in electrical communication with the integrated circuits;

a plurality of conductive grooves in the peripheral edge in electrical communication with the first pads;

a plurality of second pads on the second side in electrical communication with the conductive grooves;

a plurality of first conductors on the first side in electrical communication with the first pads and the conductive grooves and a plurality of second conductors on the second side in electrical communication with the second pads and the conductive grooves; and

a second package substantially identical to the package, stacked on the package and bonded to the first pads or to the second pads.

28. The assembly of claim 27 further comprising an adhesive polymer layer bonding the package to the second package.

29. The assembly of claim 27 further comprising an anisotropic conductive adhesive layer bonding the package to the second package.

30. The assembly of claim 27 further comprising a plurality of external contacts on the second pads and a supporting substrate having a plurality of electrodes bonded to the external contacts.

31. The assembly of claim 27 further comprising a supporting substrate and an anisotropic conductive adhesive layer bonding the package to the supporting substrate.

32. The assembly of claim 27 wherein each first pad includes a bump or a ball.

33. The assembly of claim 27 wherein each second pad includes a bump or a ball.

34. The assembly of claim 27 wherein the conductive grooves comprise arcuate or semicircular openings and a conductive material in the openings.

35. The assembly of claim 27 further comprising a plurality of circuit side conductors on the first surface in electrical communication with the first pads and a plurality of back side conductors on the second surface in electrical communication with the second pads.

36. A stacked semiconductor assembly comprising:

a first package and a second package each package comprising;

a semiconductor die comprising a plurality of integrated circuits and having a circuit side, a back side and a peripheral edge;

a plurality of stacking pads on the first side in a selected pattern in electrical communication with the integrated circuits;

a plurality of stacking contacts on the second side in the selected pattern in electrical communication with the stacking pads;

a plurality of conductive grooves in the peripheral edge configured as interlevel conductors between the stacking pads and the stacking contacts; and

a plurality of circuit side conductors on the circuit side in electrical communication with the stacking pads and the conductive grooves and a plurality of back side conductors on the back side in electrical communication with the stacking contacts and the conductive grooves;

the first package stacked to the second package with the stacking contacts on the first package bonded to the stacking pads on the second package.

37. The assembly of claim 36 further comprising a polymer adhesive layer bonding the first package to the second package.

38. The assembly of claim 36 further comprising a conductive polymer adhesive layer bonding the first package to the second package.

39. The assembly of claim 36 wherein the conductive grooves comprise collinear pairs on opposing edges of the die.