Circuit for improving noise immunity by DV/DT boosting

• US 6,611,154 B2
• Filed: 06/28/2002
• Issued: 08/26/2003
• Est. Priority Date: 07/02/2001
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Subaramanian, Muthu, Grasso, Massimo
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US10/186,554
• Publication Number:
  US 20030001609A1
• Time in Patent Office: 424 Days
• Field of Search: 326/80-83, 326/86, 326/26-27, 326/31, 326/34
• US Class Current: 326/83
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

A circuit for suppressing false operation of a level shift circuit due to a noise transient, the circuit comprising a first transistor coupled to a voltage source of the level shift circuit and being coupled to pass a current when a noise transient is present on the voltage source an output terminal coupled to the first transistor providing as an injected signal a current proportional to the current in the first transistor to at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

Claims

1. A circuit for suppressing false operation of a level shift circuit due to a noise transient, the circuit comprising:

a first transistor coupled to a voltage source of the level shift circuit and being coupled to pass a current when a noise transient is present on said voltage source; and

an output terminal coupled to the first transistor providing as an injected signal a current proportional to said current in said first transistor to at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

2. The circuit of claim 1, further comprising:

a capacitance element that simulates a parasitic capacitance of a transistor in the level shift circuit;

the first transistor being coupled in series with the capacitance element and having a control input coupled to the voltage source of the level shift circuit affected by the noise transient,

further comprising a further transistor coupled to the first transistor as a current mirror for mirroring the current flowing in the first transistor; and

the output terminal providing as the injected signal a current flowing in said further transistor mirroring the current in the first transistor to the at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

3. The circuit of claim 2, wherein the capacitance element comprises a second transistor.

4. The circuit of claim 2, further comprising a delay circuit coupled to said first and further transistors for delaying the current flowing through said first and further transistors and determining a duration of the injected signal.

5. The circuit of claim 4, wherein the delay circuit comprises an RC circuit.

6. The circuit of claim 5, wherein the RC circuit comprises a resistor and an additional transistor coupled in series.

7. The circuit of claim 6, wherein a common connection of the resistor and additional transistor is coupled to the control input of the first and further transistors.

8. The circuit of claim 6, wherein the first, second, further and additional transistors comprises FETs.

9. The circuit of claim 1, wherein the injected signal is provided to a drain node of the at least one level shift transistor of the level shift circuit.

10. The circuit of claim 1, wherein the injected signal is provided to a drain node of the at least one level shift transistor of the level shift circuit, which drain node is in a high state to ensure that the node stays high during the noise transient.

11. A circuit for suppressing false operation of a level shift circuit due to a noise transient, the circuit comprising:

a first transistor having a control input coupled to a voltage source of the level shift circuit affected by the noise transient,

a second transistor coupled in series with the first transistor and which simulates a parasitic capacitance of a transistor in the level shift circuit;

a third transistor coupled to the first transistor as a current mirror for mirroring a current flowing in the first transistor; and

an output terminal providing as an injected signal a current flowing in said third transistor mirroring the current in the first transistor and coupled to at least one level shift transistor in the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

12. The circuit of claim 11, further comprising a delay circuit coupled to said first and third transistor for delaying the current flowing through said first and third transistors and determining a duration of the injected signal.

13. The circuit of claim 12, wherein the delay circuit comprises an RC circuit.

14. The circuit of claim 13, wherein the RC circuit comprises a resistor and a fourth transistor coupled in series.

15. The circuit of claim 14, wherein a common connection of the resistor and fourth transistor is coupled to the control input of the first and third transistors.

16. The circuit of claim 14, wherein the first, second, third and fourth transistors comprises FETs.

17. The circuit of claim 11, wherein the injected signal is provided to a drain node of the at least one level shift transistor of the level shift circuit.

18. The circuit of claim 11, wherein the injected signal is provided to a drain node of the at least one level shift transistor of the level shift circuit, which drain node is in a high state to ensure that the node stays high during the noise transient.

19. A method for suppressing false operation of a level shaft circuit due to a noise transient, the method comprising:

providing a first transistor having a control input coupled to a voltage source of the level shift circuit affected by the noise transient and passing a current through the first transistor in response to the noise transient present on the voltage source; and

providing an injection signal in response to said current in the first transistor to at least one level shift transistor of the level shift circuit to prevent false trigering of the level shift circuit due to the noise transient.

20. The method of claim 19, further comprising:

providing a capacitance element that simulates a parasitic capacitance of a transistor in the level shift circuit;

providing a further transistor coupled to the first transistor as a current mirror for mirroring the current flowing in the first transistor; and

providing as the injected signal a current flowing in said further transistor mirroring the current in the first transistor and coupled to the at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

21. The method of claim 20, further comprising delaying the current flowing through said first and further transistors and determining a duration of the injected signal.

22. The method of claim 20, wherein the step of providing a capacitance element comprises using an FET as a capacitance element.

23. The method of claim 19, wherein the step of providing an injection signal comprises providing the injection signal to a drain node of the at least one level shift transistor of the level shift circuit.

24. The method of claim 19, wherein the step of providing an injection signal comprises providing the injection signal to a drain node of the at least one level shift transistor of the level shift circuit, which drain node is in a high state to ensure that the node stays high during the noise transient.