Architecture for decimation algorithm

• US 6,611,220 B1
• Filed: 10/09/2001
• Issued: 08/26/2003
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): JeanPierre, Peguy
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US09/973,535
• Time in Patent Office: 686 Days
• Field of Search: 341/143, 341/144, 341/118, 341/120, 708/313
• US Class Current: 341/143
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A new architecture for implementing a digital algorithm such as a decimation algorithm is described. The new decimator circuit is well suited for digital circuits such as a delta-sigma (or sigma-delta) analog-to-digital converter. In particular, the new decimator circuit incorporates a general purpose architecture which enables a wide range of flexibility to change and modify the decimation algorithm performed by the decimator circuit. Moreover, the new decimator circuit can be fabricated in a smaller chip area than previously possible.

Claims

1. A circuit comprising:

a multiplexer having a plurality of multiplexed inputs and a multiplexer output for outputting one of said multiplexed inputs, wherein one of said multiplexed inputs is coupled to a input signal;

an adder having a first input, a second input, and an adder output, wherein said second input receives one of said multiplexed inputs outputted by said multiplexer output; and

a random access memory (RAM) having a plurality of memory locations, a first output port coupled to said first input of said adder, a second output port coupled to one of said multiplexed inputs of said multiplexer, an input port coupled to said adder output, a first address port for selecting one of said memory locations to couple to said first output port and to said input port, and a second address port for selecting one of said memory locations to couple to said second output port, wherein said multiplexer, said adder, and said RAM perform in a clock cycle at least a portion of a stage of a digital algorithm.

2. A circuit as recited in claim 1 wherein said digital algorithm is a decimation algorithm, and further comprising a state machine operative to generate a plurality of signals for controlling operation of said multiplexer, said adder, and said RAM such that to perform said decimation algorithm.

3. A circuit as recited in claim 2 wherein said plurality of signals includes a selection signal for selecting one of said multiplexed inputs of said multiplexer, an inversion signal for indicating whether to generate a negative version of said selected one of said multiplexed inputs at said multiplexer output, a carry-in signal for said adder, a first address signal for said first address port of said RAM, and a second address signal for said second address port of said RAM.

4. A circuit as recited in claim 1 wherein said digital algorithm is a decimation algorithm, and further comprising a controller operative to generate a plurality of signals for controlling operation of said multiplexer, said adder, and said RAM such that to perform said decimation algorithm.

5. A circuit as recited in claim 4 wherein said plurality of signals includes a selection signal for selecting one of said multiplexed inputs of said multiplexer, an inversion signal for indicating whether to generate a negative version of said selected one of said multiplexed inputs at said multiplexer output, a carry-in signal for said adder, a first address signal for said first address port of said RAM, and a second address signal for said second address port of said RAM.

6. A circuit as recited in claim 1 further comprising a register disposed between said multiplexer output and said second input of said adder.

7. A circuit as recited in claim 1 wherein said input signal has one of a +1 value and a −

1 value.

8. A decimator circuit comprising:

a multiplexer having a plurality of multiplexed inputs and a multiplexer output for outputting one of said multiplexed inputs, wherein one of said multiplexed inputs is coupled to a input signal;

an adder having a first input, a second input, and an adder output, wherein said second input receives one of said multiplexed inputs outputted by said multiplexer output; and

a random access memory (RAM) having a plurality of memory locations, a first output port coupled to said first input of said adder, a second output port coupled to one of said multiplexed inputs of said multiplexer, an input port coupled to said adder output, a first address port for selecting one of said memory locations to couple to said first output port and to said input port, and a second address port for selecting one of said memory locations to couple to said second output port, wherein said multiplexer, said adder, and said RAM perform in a clock cycle at least a portion of a stage of a decimation algorithm.

9. A decimator circuit as recited in claim 8 further comprising a state machine operative to generate a plurality of signals for controlling operation of said multiplexer, said adder, and said RAM such that to perform said decimation algorithm.

10. A decimator circuit as recited in claim 9 wherein said plurality of signals includes a selection signal for selecting one of said multiplexed inputs of said multiplexer, an inversion signal for indicating whether to generate a negative version of said selected one of said multiplexed inputs at said multiplexer output, a carry-in signal for said adder, a first address signal for said first address port of said RAM, and a second address signal for said second address port of said RAM.

11. A decimator circuit as recited in claim 8 further comprising a controller operative to generate a plurality of signals for controlling operation of said multiplexer, said adder, and said RAM such that to perform said decimation algorithm.

12. A decimator circuit as recited in claim 11 wherein said plurality of signals includes a selection signal for selecting one of said multiplexed inputs of said multiplexer, an inversion signal for indicating whether to generate a negative version of said selected one of said multiplexed inputs at said multiplexer output, a carry-in signal for said adder, a first address signal for said first address port of said RAM, and a second address signal for said second address port of said RAM.

13. A decimator circuit as recited in claim 8 further comprising a register disposed between said multiplexer output and said second input of said adder.

14. A decimator circuit as recited in claim 8 wherein said input signal has one of a +1 value and a −

1 value.

15. A delta-sigma analog-to-digital converter comprising:

a decimator circuit including;

a multiplexer having a plurality of multiplexed inputs and a multiplexer output for outputting one of said multiplexed inputs, wherein one of said multiplexed inputs is coupled to a input signal;

an adder having a first input, a second input, and an adder output, wherein said second input receives one of said multiplexed inputs outputted by said multiplexer output; and

a random access memory (RAM) having a plurality of memory locations, a first output port coupled to said first input of said adder, a second output port coupled to one of said multiplexed inputs of said multiplexer, an input port coupled to said adder output, a first address port for selecting one of said memory locations to couple to said first output port and to said input port, and a second address port for selecting one of said memory locations to couple to said second output port, wherein said multiplexer, said adder, and said RAM perform in a clock cycle at least a portion of a stage of a decimation algorithm.

16. A delta-sigma analog-to-digital converter as recited in claim 15 wherein said decimator circuit further comprises a state machine operative to generate a plurality of signals for controlling operation of said multiplexer, said adder, and said RAM such that to perform said decimation algorithm.

17. A delta-sigma analog-to-digital converter as recited in claim 16 wherein said plurality of signals includes a selection signal for selecting one of said multiplexed inputs of said multiplexer, an inversion signal for indicating whether to generate a negative version of said selected one of said multiplexed inputs at said multiplexer output, a carry-in signal for said adder, a first address signal for said first address port of said RAM, and a second address signal for said second address port of said RAM.

18. A delta-sigma analog-to-digital converter as recited in claim 15 wherein said decimator circuit further comprises a controller operative to generate a plurality of signals for controlling operation of said multiplexer, said adder, and said RAM such that to perform said decimation algorithm.

19. A delta-sigma analog-to-digital converter as recited in claim 18 wherein said plurality of signals includes a selection signal for selecting one of said multiplexed inputs of said multiplexer, an inversion signal for indicating whether to generate a negative version of said selected one of said multiplexed inputs at said multiplexer output, a carry-in signal for said adder, a first address signal for said first address port of said RAM, and a second address signal for said second address port of said RAM.

20. A delta-sigma analog-to-digital converter as recited in claim 15 wherein said decimator circuit further comprises a register disposed between said multiplexer output and said second input of said adder.

21. A delta-sigma analog-to-digital converter as recited in claim 15 wherein said input signal has one of a +1 value and a −

1 value.