Ultra-high bandwidth multi-port memory system for image scaling applications

• US 6,611,260 B1
• Filed: 05/17/1999
• Issued: 08/26/2003
• Est. Priority Date: 11/24/1997
• Status: Active Grant

• Current Assignee: Pixelworks Incorporated
• Original Assignee: Pixelworks Incorporated
• Inventors: Greenberg, Robert Y., West, Michael G.
• Primary Examiner(s): Shankar, Vijay
• Application Number:
  US09/313,060
• Time in Patent Office: 1,562 Days
• Field of Search: 345/212, 345/213, 345/196, 345/204, 345/536, 345/545, 345/558, 345/560, 345/660, 345/667, 345/668, 345/669, 345/670, 345/671
• US Class Current: 345/204
• CPC Class Codes: G06T 3/4023 based on decimating pixels or lines of pixels; based on inserting pixels or lines of pixels
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers. The plurality of output buffers provides the vertical scalar with simultaneous parallel access to multiple lines of buffered digital image data. The frame memory preferably comprises DRAM that stores the image data such that row faults are minimized. The DRAM frame memory preferably includes at least two memory banks, each including a plurality of rows and a plurality of columns. The DRAM frame memory has multiple purposes including storing digital image data frames for sample rate conversion, as well as, storing bitmaps for access by an On Screen Display controller and storing microprocessor data for access by a microprocessor.

Claims

1. A pixelated display controller integrated circuit, comprising:

an image scalar circuit for vertically scaling digital data of a pixelated image;

a frame memory coupled to the image scaling circuit adapted to store digital image data frames; and

a plurality of buffers positioned between the image scalar and the frame memory, each buffer storing a corresponding portion of the digital image data frame such that the image scalar circuit parallel accesses the portions of the digital image data frame stored in the plurality of buffers.

2. The pixelated display controller of claim 1 wherein the image scalar circuit includes a vertical scalar circuit for scaling the digital image data in a vertical direction.

3. The pixelated display controller of claim 1 wherein the frame memory comprises DRAM memory.

4. The pixelated display controller of claim 3 wherein the frame memory includes an image portion for storing the digital image frames, an OSD portion for storing OSD bitmaps for access by an OSD controller, a microprocessor portion for storing microprocessor data for access by a microprocessor, or a combination thereof.

5. The pixelated display controller of claim 3 wherein the frame memory comprises at least two memory banks, each bank including a plurality of rows and columns, each row storing portions of a plurality of lines of the digital image data.

6. The pixelated display controller of claim 5 wherein each row stores portions of a plurality of digital data lines such that corresponding portions of sequential digital data lines are stored in no more than one row in each bank thereby minimizing row faults.

7. The pixelated display controller of claim 1 including an input buffer coupled to an input side of the frame memory for buffering the digital image data.

8. The pixelated display controller of claim 1 wherein each buffer sequentially accesses the frame memory and buffers portions of the corresponding digital image data lines transferred from the frame memory.

9. The pixelated display controller of claim 1 wherein each buffer is a FIFO buffer.

10. A vertical scaling circuit for vertically scaling digital data of a pixelated image, comprising:

a frame memory for storing the digital data, the digital data being divided into a plurality of frames, each frame including a plurality of lines;

a plurality of output buffers, each output buffer adapted to store at least a portion of a selected line; and

a vertical scalar coupled to the plurality of output buffers adapted to vertically scale the pixelated image by parallel accessing the portions of the selected lines stored in each of the output buffers;

wherein the frame memory, the plurality of output buffers, and the vertical scalar are embedded in an integrated circuit.

11. The vertical scaling circuit of claim 10 wherein the frame memory comprises DRAM-type memory.

12. The vertical scaling circuit of claim 11 wherein the frame memory comprises at least two memory banks, each bank including a plurality of rows and columns, each row storing portions of sequential digital data lines.

13. The vertical scaling circuit of claim 12 wherein each row stores portions of sequential digital data lines such that corresponding portions of sequential digital data lines are stored in no more than one row in each bank thereby minimizing row faults.

14. The vertical scaling circuit of claim 11 wherein the frame memory includes an image portion for storing the digital image frames, an OSD portion for storing OSD bitmaps for access by an OSD controller, a microprocessor portion for storing microprocessor data for access by a microprocessor, or a combination thereof.

15. The vertical scaling circuit of claim 10 wherein the frame memory includes a single output port and wherein each output buffer sequentially accesses the frame memory through the output port.

16. The vertical scaling circuit of claim 10 wherein each output buffer is a FIFO buffer.

17. The vertical scaling circuit of claim 10 wherein the plurality of output buffers includes an input bandwidth and an output bandwidth, the input bandwidth being equal to or greater than the output bandwidth.

18. The vertical scaling circuit of claim 10 including an input buffer coupled to an input side of the frame memory for buffering the digital data, the input buffer being embedded in the integrated circuit.

19. The vertical scaling circuit of claim 18 wherein the input buffer is a FIFO buffer.

20. A method for vertically scaling digital data representative of a pixelated digital image, comprising:

embedding a frame memory and a vertical scalar in an integrated circuit;

storing the digital data in the frame memory;

transferring portions of selected digital data lines from the frame memory to a corresponding output buffer until a plurality of output buffers stores corresponding portions of sequential digital data lines; and

scaling the pixelated digital image with the vertical scalar by parallel accessing the portions of selected data lines stored in the plurality of output buffers.

21. The method of claim 20 wherein storing the digital data in the frame memory includes storing the digital data in a DRAM memory.

22. The method of claim 21 wherein storing the digital data in a DRAM frame buffer includes storing the digital data in at least two memory banks, each bank including a plurality of rows and columns, each row storing corresponding portions of sequential digital data lines.

23. The method of claim 22 wherein storing the digital data in at least two memory banks includes storing the data in the plurality of rows such that corresponding portions of sequential digital data lines are stored in no more than one row in each bank thereby minimizing row faults.

24. The method of claim 21 wherein storing the digital data in the frame memory includes storing a digital data frame in the frame memory for conversion from an input refresh rate to an output refresh rate, storing OSD bitmaps in the frame memory, or storing microprocessor data in the frame memory.

25. The method of claim 20 wherein the frame memory includes an output port and wherein transferring portions of selected digital data lines includes having each output buffer sequentially access the output port.

26. The method of claim 20 wherein transferring portions of digital data lines includes transferring portions of digital data lines from the frame memory to a corresponding FIFO output buffer.

27. The method of claim 20 including buffering the data in an input buffer.

28. The method of claim 27 wherein buffering the data in an input buffer includes buffering the data in a FIFO input buffer.

29. The method of claim 20 wherein transferring portions of selected digital data lines occurs at a higher bandwidth than scaling the pixelated image by accessing the portions of selected digital lines.