Method and system for dual reticle image exposure

• US 6,611,316 B2
• Filed: 02/27/2002
• Issued: 08/26/2003
• Est. Priority Date: 02/27/2001
• Status: Active Grant

• Current Assignee: ASML Holding NV
• Original Assignee: ASML Holding NV
• Inventors: Sewell, Harry
• Primary Examiner(s): Adams, Russell
• Assistant Examiner(s): ESPLIN, DAVID B
• Application Number:
  US10/083,667
• Publication Number:
  US 20020123012A1
• Time in Patent Office: 545 Days
• Field of Search: 355/46, 355/52, 355/66, 355/53
• US Class Current: 355/46
• CPC Class Codes: G03F 7/70283 Mask effects on the imaging process
• CPC Class Codes: G03F 7/70358 Scanning exposure, i.e. relative movement of patterned beam and workpiece during imaging

Abstract

The present invention provides a method and system for simultaneously imaging at least two reticles onto a substrate. According to the present invention, the wafer is passed through the exposure sequence once with images from the reticles being exposed simultaneously onto the wafer. The throughput of the system is effectively maintained at the standard single pass throughput level or twice that of conventional systems. In one embodiment, the present invention produces two reticle images side-by-side in the exit pupil of the optics of a step and scan wafer exposure system. The scanning action of the exposure tool then effectively superimposes the two images during the exposure of the wafer. Each image exposes the photoresist as the wafer is scanned through the image field synchronously with the scanning of the reticles. According to one embodiment, the image scanning is synchronized so that two required images are superimposed. According to another embodiment, the two images can be independently focused and aligned.

Claims

1. A lithographic system, comprising:

a scanning stage that controls one or more reticles, and having a range of motion that permits scanning of at least two patterns formed on said one or more reticles simultaneously;

projection optics positioned relative to said one or more reticles to simultaneously project images corresponding to said at least two patterns; and

a substrate stage positioned relative to said projection optics to receive said images corresponding to said at least two patterns simultaneously projected from said projection optics,

wherein said scanning stage positions said images corresponding to at least a portion of each of said at least two patterns to simultaneously project each of said images at an image field on said substrate stage such that combining projections of said images is not required prior to exposure at said image field on said substrate stage.

2. A lithographic system of claim 1, wherein said images corresponding to said at least two patterns are images from different locations of one of said one or more reticles.

3. A lithographic system of claim 1, further comprising:

a calibration detector on said substrate stage to receive said images corresponding to said at least two patterns from said scanning stage, wherein real-time system calibration is obtained.

4. A lithographic system of claim 1, wherein said substrate stage contains at least one resist coated wafer.

5. A lithographic system of claim 1, wherein at least one of said images corresponding to said at least two patterns formed on said one or more reticles comprise an image of an integrated circuit pattern.

6. A lithographic system of claim 1, wherein one of said at least two patterns formed on said one or more reticles comprises a phase-shift pattern.

7. A lithographic system of claim 1, wherein said scanning stage includes one or more pupil filters that independently condition said images corresponding to said at least two patterns.

8. A method of exposing a field on a substrate stage with images from at least two patterns, formed on at least one reticle, comprising:

a) positioning a scanning stage that includes the at least one reticle;

b) positioning an image field on a substrate stage, wherein said image field results from projection optics positioned relative to said scanning stage and said substrate stage; and

c) scanning images corresponding to said at least two patterns simultaneously from said scanning stage to simultaneously project each of said images at said image field on said substrate stage such that combining projections of said images is not required prior to exposure at said image field on said substrate stage.

9. The method of claim 8, further comprising:

d) superimposing said one or more images in said image field on said substrate stage.

10. The method of claim 8, further comprising:

e) exposing a resist coated wafer positioned on said substrate stage.

11. The method of claim 8, providing said scanning step c) further includes the step of conditioning said images corresponding to said at least two patterns independently.

12. The method of claim 8, providing at least two of the at least two patterns are the same pattern.

13. The method of claim 8, providing at least one of the at least two patterns contains integrated circuit patterns.

14. The method of claim 8, providing one of the at least two patterns is a phase-shift pattern.