Electronic assembly comprising substrate with embedded capacitors

• US 6,611,419 B1
• Filed: 07/31/2000
• Issued: 08/26/2003
• Est. Priority Date: 07/31/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chakravorty, Kishore K.
• Primary Examiner(s): Reichard, Dean A.
• Assistant Examiner(s): HA, NGUYEN T
• Application Number:
  US09/631,037
• Time in Patent Office: 1,121 Days
• Field of Search: 361/306.3, 361/313, 361/763, 361/219, 361/321.2, 361/306.1, 361/312, 361/320, 361/738, 361/309, 361/307, 361/308.3, 361/329, 361/330
• US Class Current: 361/306.3
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0187 with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/4611 by laminating two or more circuit boards H05K3/4652 takes precedence
• CPC Class Codes: H05K 3/4629 : laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
• CPC Class Codes: H05K 3/4688 : Composite multilayer circuits, i.e. comprising insulating layers having different properties having a special base or central core H05K3/4602

Abstract

To reduce switching noise, the power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate. In one embodiment, the capacitor is formed of at least one high permittivity layer. In another embodiment, several high permittivity layers are interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Claims

1. A multilayer ceramic substrate for mounting a die comprising:

an embedded capacitor having first and second terminals;

a first surface having a first core including a first plurality of power lands coupled to the first terminal and a first plurality of ground lands coupled to the second terminal, the first plurality of power lands and the first plurality of ground lands each being a relatively large number, and a first periphery comprising a first plurality of signal lands; and

a second surface having a second core including a second plurality of power lands coupled to the first terminal and a second plurality of ground lands coupled to the second terminal, and a second periphery comprising a second plurality of signal lands;

wherein the first plurality of power lands, the first plurality of ground lands, and the first plurality of signal lands are positioned to be coupled to corresponding power, ground, and signal nodes of the die.

2. The multilayer ceramic substrate recited in claim 1, wherein the second plurality of power lands, the second plurality of ground lands, and the second plurality of signal lands are positioned to be coupled to corresponding power, ground, and signal nodes of an additional substrate subjacent to the multilayer ceramic substrate.

3. The multilayer ceramic substrate recited in claim 1, wherein the embedded capacitor comprises at least one high permittivity layer.

4. The multilayer ceramic substrate recited in claim 1 wherein the embedded capacitor comprises a plurality of high permittivity layers.

5. The multilayer ceramic substrate recited in claim 4 wherein the embedded capacitor comprises a plurality of conductive layers interleaved with the high permittivity layers, such that alternating conductive layers are coupled to the first and second terminals , respectively.

6. The multilayer ceramic substrate recited in claim 1 wherein the embedded capacitor comprises at least one embedded discrete capacitor.

7. The multilayer ceramic substrate recited in claim 1 wherein at least one of the first plurality of power lands is coupled to the first terminal through a via that does not go entirely through the multilayer ceramic substrate.

8. The multilayer ceramin substrate recited in claim 1 wherein at least one of the second plurality of ground lands is coupled to the second terminal through a via that does not go entirely through the multilayer ceramic substrate.

9. An electronic assembly comprising:

a die comprising power, ground, and signal nodes; and

a multilayer ceramic substrate comprising;

an embedded capacitor having first and second terminals;

a first surface having a first core including a first plurality of power lands coupled to the first terminal and a first plurality of ground lands coupled to the second terminal, the first plurality of power lands and the first plurality of ground lands each being a relatively large number, and a first periphery comprising a first plurality of signal lands; and

a second surface having a second core including a second plurality of power lands coupled to the first terminal and a second plurality of ground lands coupled to the second terminal, and a second periphery comprising a second plurality of signal lands;

wherein the first plurality of power lands, the first plurality of ground lands, and the first plurality of signal lands are coupled to corresponding ones of the power, ground, and signal nodes of the die.

10. The electronic assembly recited in claim 9 wherein the embedded capacitor comprises at least one high permittivity layer.

11. The electronic assembly recited in claim 9 wherein the embedded capacitor comprises a plurality of high permittivity layers.

12. The electronic assembly recited in claim 11 wherein the embedded capacitor comprises a plurality of conductive layers interleaved with the high permittivity layers, such that alternating conductive layers are coupled to the first and second terminals , respectively.

13. The electronic assembly recited in claim 9 wherein the embedded capacitor comprises at least one embedded discrete capacitor.

14. The electronic assembly recited in claim 9 wherein at least one of the first plurality of power lands is coupled to the first terminal through a via that does not go entirely through the multilayer ceramic substrate.

15. The electronic assembly recited in claim 9 wherein at least one of the second plurality of ground lands is coupled to the second terminal through a via that does not go entirely through the multilayer ceramic substrate.

16. An electronic system comprising an electronic assembly having a die coupled to a

multilayer ceramic substrate, the die comprising power, ground, and signal nodes, and the

substrate including

at least one embedded capacitor having first and second terminals;

a first surface having a first core including a first plurality of power lands coupled to the first terminal and a first plurality of ground lands coupled to the second terminal, the first plurality of power lands and the first plurality of ground lands each being a relatively large number, and a first periphery comprising a first plurality of signal lands; and

a second surface having a second core including a second plurality of power lands coupled to the first terminal and a second plurality of ground lands coupled to the second terminal, and a second periphery comprising a second plurality of signal lands;

wherein the first plurality of power lands, the first plurality of ground lands, and the first plurality of signal lands are coupled to corresponding power, ground, and signal nodes of the die.

17. The electronic system recited in claim 16 wherein the at least one embedded capacitor comprises at least one high permittivity layer.

18. The electronic system recited in claim 16 wherein the at least one embedded capacitor comprises a plurality of high permittivity layers.

19. The electronic system recited in claim 18 wherein the at least one embedded capacitor comprises a plurality of conductive layers interleaved with the high permittivity layers, such that alternating conductive layers are coupled to the first and second terminals, respectively.

20. The electronic system recited in claim 16 wherein the at least one embedded capacitor comprises at least one embedded discrete capacitor.

21. The electronic assembly recited in claim 16 wherein at least one of the first plurality of power lands is coupled to the first terminal through a via that does not go entirely through the multilayer ceramic substrate.

22. The electronic assembly recited in claim 16 wherein at least one of the second plurality of ground lands is coupled to the second terminal through a via that does not go entirely through the multilayer ceramic substrate.

23. A substrate to package a die comprising:

a plurality of power and ground vias in a core region of the substrate;

a plurality of signal vias in a peripheral region of the substrate;

an embedded capacitor having first and second terminals; and

a surface having a plurality of power lands coupled to the first terminal through the plurality of power vias, a plurality of ground lands coupled to the second terminal through the plurality of ground vias, and a plurality of signal lands coupled to the plurality of signal vias;

wherein the plurality of power lands, the plurality of ground lands, and the plurality of signal lands are positioned to be coupled to corresponding power, ground, and signal nodes of the die through controlled collapse chip connect (C4) solder bumps, and wherein the plurality of power lands and the plurality of ground lands are each a relatively large number.

24. The substrate recited in claim 23, wherein the substrate is a multilayer ceramic substrate.

25. The substrate recited in claim 23, wherein at least one of the power vias does not go entirely through the substrate.

26. The substrate recited in claim 23, wherein at least one of the ground vias does not go entirely through the substrate.

27. A substrate to package a die comprising:

a plurality of power and ground vias in a core region of the substrate;

an embedded capacitor having first and second terminals;

a first surface including a first plurality of power lands coupled to the first terminal through first ones of the plurality of power vias, and a first plurality of ground lands coupled to the second terminal through first ones of the plurality of ground vias;

a second surface including a second plurality of power lands coupled to the first terminal through second ones of the plurality of power vias, and a second plurality of ground lands coupled to the second terminal through second ones of the plurality of ground vias;

wherein the first plurality of power lands and the first plurality of ground lands are positioned to be coupled to corresponding power and ground nodes of the die through controlled collapse chip connect (C4) solder bumps.

28. The substrate recited in claim 27, wherein the substrate is a multilayer ceramic substrate.

29. The substrate recited in claim 27, wherein the first plurality of power lands and the first plurality of ground lands are each a relatively large number.

30. The substrate recited in claim 27, wherein at least one of the power vias does not go entirely through the substrate.

31. The substrate recited in claim 27, wherein at least one of the ground vias does not go entirely through the substrate.

32. A substrate to package a die comprising:

a plurality of power and ground vias in a core region of the substrate;

a plurality of signal vias;

an embedded capacitor having first and second terminals;

a first surface including a first plurality of power lands coupled to the first terminal through first ones of the plurality of power vias, a first plurality of ground lands coupled to the second terminal through first ones of the plurality of ground vias, and a first plurality of signal lands coupled to the plurality of signal vias;

a second surface including a second plurality of power lands coupled to the first terminal through second ones of the plurality of power vias, a second plurality of ground lands coupled to the second terminal through second ones of the plurality of ground vias, and a second plurality of signal lands coupled to the plurality of signal vias;

wherein the first plurality of power lands, the first plurality of ground lands, and the first plurality of signal lands are positioned to be coupled to corresponding power, ground, and signal nodes of the die through controlled collapse chip connect (C4) solder bumps.

33. The substrate recited in claim 32, wherein the substrate is a multilayer ceramic substrate.

34. The substrate recited in claim 32, wherein the first plurality of power lands and the first plurality of ground lands are each a relatively large number.

35. The substrate recited in claim 32, wherein at least one of the power vias does not go entirely through the substrate.

36. The substrate recited in claim 32, wherein at least one of the ground vias does not go entirely through the substrate.

37. The substrate recited in claim 32, wherein the plurality of signal vias are in a peripheral region of the substrate.