Memory array and wordline driver supply voltage differential in standby

• US 6,611,451 B1
• Filed: 06/28/2002
• Issued: 08/26/2003
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US10/185,380
• Time in Patent Office: 424 Days
• Field of Search: 365/189.09, 365/200, 365/201, 365/230.02, 365/230.03, 365/230.06, 365/154, 365/156
• US Class Current: 365/154
• CPC Class Codes: G11C 11/418 Address circuits

Abstract

An SRAM array 22, with improved leakage in standby, raises the wordline driver lower supply voltage Vss-WL when raising the array lower supply voltage Vss-array in standby. When the SRAM array 22 is in active mode, a source voltage is provided to the SRAM array lower supply node Vss-array and to the wordline driver lower supply node Vss-WL. When the SRAM array is in standby mode, a voltage offset is provided between the source voltage and both the SRAM array lower supply node Vss-array and the wordline driver lower supply node Vss-WL.

Claims

1. A circuit comprising:

a memory array having an array supply voltage node;

a wordline driver coupled to the memory array and having a wordline driver supply voltage node, wherein the wordline driver supply voltage node is coupled to the array supply voltage node;

a first offset voltage device coupled between the wordline driver supply voltage node and a first source voltage node;

a first bypass switch coupled between the wordline driver and a second source voltage node; and

a second offset voltage device coupled between the array supply voltage node and the wordline driver supply voltage node.

2. The circuit of claim 1 wherein the first source voltage node is coupled to the second source voltage node.

3. The circuit of claim 1 wherein the first bypass switch is on when the memory array is in active mode.

4. The circuit of claim 1 wherein the first bypass switch is off when the memory array is in standby mode.

5. The circuit of claim 1 wherein the first bypass switch is on when the memory array is in active mode and off when the memory array is in standby mode.

6. The circuit of claim 1 wherein the memory array is an SRAM array.

7. The circuit of claim 1 wherein the first offset voltage device is a diode.

8. The circuit of claim 1 wherein the first offset voltage device is a transistor.

9. The circuit of claim 1 wherein the first bypass switch is a transistor.

10. The circuit of claim 1 further comprising a second bypass switch coupled between the array supply voltage node and the second source voltage node.

11. The circuit of claim 10 wherein the first bypass switch has a control node coupled to a first control signal, and the second bypass switch has a control node coupled to a second control signal.

12. The circuit of claim 1 wherein the second offset voltage device is a transistor.