Reference cells for TCCT based memory cells

• US 6,611,452 B1
• Filed: 04/05/2002
• Issued: 08/26/2003
• Est. Priority Date: 04/05/2002
• Status: Expired due to Fees

• Current Assignee: T-Ram, LLC
• Original Assignee: T-Ram, Inc.
• Inventors: Han, Jin-Man
• Primary Examiner(s): Lam, David
• Application Number:
  US10/117,930
• Time in Patent Office: 508 Days
• Field of Search: 365/159, 365/71, 365/72, 365/175, 365/148, 365/149
• US Class Current: 365/159
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A reference cell produces a voltage rise on a bit line that is proportional to, and preferably half of, the voltage rise on another bit line produced by a TCCT based memory cell in an “on” state. The reference cell includes an NDR device, a gate-like device disposed adjacent to the NDR device, a first resistive element coupled between the NDR device and the bit line, and a second resistive element coupled between a sink and the bit line. Resistances of the first and second resistive elements are about equal and about twice as much as the resistance of a pass transistor of the a TCCT based memory cell.

Claims

1. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source comprising a NDR device;

a first resistive element coupled between the voltage source and a bit line and having a first resistance; and

a second resistive element coupled between a sink and the bit line and having a second resistance.

2. The reference cell of claim 1 further including a gate-like device disposed adjacent to the NDR device and wherein the NDR device includes an anode and a cathode.

3. The reference cell of claim 2 wherein a word line connects the anode of the NDR device and the gate-like device.

4. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source comprising a SRAM memory cell;

a first resistive element coupled between the voltage source and a bit line and having a first resistance; and

a second resistive element coupled between a sink and the bit line and having a second resistance.

5. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source comprising a MRAM memory cell;

a first resistive element coupled between the voltage source and a bit line and having a first resistance; and

a second resistive element coupled between a sink and the bit line and having a second resistance.

6. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source comprising a memory cell with floating gate;

a first resistive element coupled between the voltage source and a bit line and having a first resistance; and

a second resistive element coupled between a sink and the bit line and having a second resistance.

7. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source;

a first transistor coupled between the voltage source and a bit line and having a first resistance; and

a second transistor coupled between a sink and the bit line and having a second resistance;

wherein both the first and the second transistors include a gate coupled to a word line.

8. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source;

a first resistive element coupled between the voltage source and a bit line and having a first resistance; and

a second resistive element coupled between a sink and the bit line and having a second resistance;

wherein the first resistive element includes two transistors coupled in series.

9. A reference cell for determining a state stored in a memory cell, comprising:

a voltage source;

a first resistive element coupled between the voltage source and a bit line and having a first resistance; and

a second resistive element coupled between a sink and the bit line and having a second resistance;

wherein the second resistive element includes two transistors coupled in series.

10. A memory device, comprising:

a memory cell configured to generate a first voltage on a first bit line and including a switching device having a first resistance;

a reference cell configured to generate a second voltage on a second bit line and including

a voltage source;

a first resistive element coupled between the voltage source and the second bit line and having a second resistance;

a second resistive element coupled between a sink and the second bit line and having a third resistance.

11. The memory device of claim 10 wherein the voltage source includes an NDR device.

12. The memory device of claim 11 wherein the reference cell further includes a gate-like device disposed adjacent to the NDR device.

13. The memory device of claim 12 wherein the reference cell further includes a first word line connecting the NDR device and the gate-like device.

14. The memory device of claim 10 further comprising means for comparing the first and second voltages.

15. The memory device of claim 10 further comprising a sense amplifier for comparing the first and second voltages.

16. The memory device of claim 10 wherein the second resistance is about twice the first resistance.

17. The memory device of claim 16 wherein the third resistance is about equal to the second resistance.

18. The memory device of claim 10 wherein the switching device is a pass transistor.

19. The memory device of claim 10 wherein memory cell is a TCCT based memory cell including an NDR device having a cathode coupled to the switching device.

20. The memory device of claim 10 wherein the first resistive element is a pass transistor.

21. The memory device of claim 20 wherein the second resistive element is a pull down transistor.

22. A memory array, comprising:

a plurality of memory cells, each memory cell configured to generate a first voltage on one of a plurality of bit lines and including a switching device having a first resistance;

a reference cell configured to generate a second voltage on another of the plurality of bit lines and including

a voltage source;

a first resistive element coupled between the voltage source and the another of the plurality of bit lines and having a second resistance;

a second resistive element coupled between a sink and the another of the plurality of bit lines and having a third resistance.

23. The memory array of claim 22 wherein the voltage source is an NDR device.

24. The memory array of claim 23 wherein the reference cell further includes a gate-like device disposed adjacent to the NDR device.

25. The memory array of claim 24 wherein the reference cell further includes a first word line connecting the NDR device and the gate-like device.

26. The memory array of claim 22 further comprising means for comparing the first and second voltages.

27. The memory array of claim 22 wherein the second resistance is about twice the first resistance.

28. The memory array of claim 27 wherein the third resistance is about equal to the second resistance.

29. The memory array of claim 22 wherein the plurality of memory cells are arranged in rows and wherein each memory cell on each row is coupled to one of said plurality of bit lines.

30. The memory array of claim 29 further comprising a plurality of reference cells.

31. The memory array of claim 30 wherein each of the plurality of reference cells is coupled to at least one of the plurality of bit lines.

32. The memory array of claim 31 wherein each of the plurality of bit lines is coupled to one of the plurality of reference cells.

33. The memory array of claim 32 further comprising a controller containing logic to select an individual memory cell connected to one of the plurality of bit lines and to select a reference cell on another one of the plurality of bit lines.

34. A method for reading a state of a memory cell, comprising:

applying a first voltage to the memory cell and a reference cell;

coupling the memory cell to a first bit line and connecting the reference cell to a second bit line;

raising a memory voltage on the first bit line;

raising on the second bit line a reference voltage that rises proportionally to the memory voltage; and

sensing a difference between the memory voltage and the reference voltage.

35. The method of claim 34 wherein the memory cell is a TCCT based memory cell.

36. The method of claim 35 wherein the state of the TCCT based memory cell is either on or off, and wherein the TCCT based memory cell in the on state can raise the memory voltage on the first bit line to maximum voltage, V.

37. The method of claim 36 wherein the reference cell can raise the reference voltage on the second bit line to maximum voltage equal to about half of V.

38. The method of claim 35 wherein the TCCT based memory cell includes a switch having a first resistance, R, the first bit line has a capacitance, C, and the reference voltage rises as a function of time, t, according to the relationship (1−

e<sup>−

t/RC</sup>).

39. The method of claim 34 wherein sensing a difference between the memory voltage and the reference voltage includes determining a polarity of the difference.