Implantable cardiac stimulation device with parameter control

• US 6,611,711 B1
• Filed: 08/27/2001
• Issued: 08/26/2003
• Est. Priority Date: 10/20/1998
• Status: Expired due to Term

• Current Assignee: St. Jude Medical AB (Abbott Laboratories)
• Original Assignee: St. Jude Medical AB (Abbott Laboratories)
• Inventors: Hedberg, Sven-Erik, Andersson, Jonas, Lidman, Johan
• Primary Examiner(s): Schaetzle, Kennedy
• Application Number:
  US09/807,803
• Time in Patent Office: 729 Days
• Field of Search: 607/9, 607/17, 607/27, 607/30, 607/31, 607/59, 607/62, 607/63
• US Class Current: 607/9
• CPC Class Codes: A61N 1/365 controlled by a physiological parameter, e.g. heart potential evoked response A61N1/371

Abstract

An implantable cardiac stimulation device operates according to a first pacing algorithm executable by a microprocessor and which is able to independently perform stimulation therapy for a patient'"'"'s heart, as well as according to a second pacing algorithm which is also microprocessor-executable. The first and second algorithms actively generate stimulation parameters during each cardiac cycle, but the stimulation parameters generated by the second algorithm are only permitted to result in actual stimulation therapy if those parameters fall within parameter ranges that are calculated to be allowable for stimulation by the first algorithm.

Claims

1. An implantable cardiac stimulation device comprising:

a stimulation administration arrangement, adapted for interaction with a patient, for administering physiological stimulation to the patient;

a memory arrangement in which a first stimulation algorithm and a second stimulation algorithm are stored; and

a microprocessor arrangement having access to said memory arrangement and connected to said stimulation administration arrangement, said microprocessor arrangement executing said first stimulation algorithm to generate stimulation parameters in each heart cycle of said patient and to calculate permissible ranges respectively for said stimulation parameters, and executing said second stimulation algorithm to generate further stimulation parameters in each heart cycle of said patient, said microprocessor controlling said stimulation administration arrangement to administer said physiological stimulation using said stimulation parameters generated by executing said first stimulation algorithm, and to instead, under predetermined conditions, administer said physiological stimulation using said stimulation parameters generated by executing said second stimulation algorithm, said predetermined conditions including a requirement that said further stimulation parameters generated by said second stimulation algorithm are within said parameter ranges.

2. An implantable cardiac stimulation device as claimed in claim 1, wherein, if said further stimulation parameters generated by executing said second stimulation algorithm are not within said parameter ranges, said microprocessor arrangement continues to control said stimulation administration arrangement to administer said physiological stimulation using said parameters generated by executing said first stimulation algorithm.

3. An implantable cardiac stimulation device as claimed in claim 1, wherein said stimulation administration arrangement includes a pulse generating circuit which generates at least one stimulation pulse as said physiological stimulation.

4. An implantable cardiac stimulation device as claimed in claim 3, wherein said pulse generating circuit generates a plurality of pacing pulses as said physiological stimulation.

5. An implantable cardiac stimulation device as claimed in claim 3, wherein said stimulation administration arrangement further comprises an input/output unit connected to said pulse generating circuit and to said microprocessor arrangement, said microprocessor arrangement writing said stimulation parameters into said input/output unit only when executing said first stimulation algorithm.

6. An implantable cardiac stimulation device as claimed in claim 1, wherein said stimulation parameters generated by executing said first stimulation algorithm represent a first stimulation therapy mode and wherein said further pacing parameters generated by executing said second stimulation algorithm represent a second stimulation therapy mode, and wherein said microprocessor arrangement, when executing said first stimulation therapy algorithm, determines, as one of said predetermined conditions, whether a switch should be made from said first stimulation therapy mode to said second stimulation therapy mode.

7. An implantable cardiac stimulation device as claimed in claim 1, wherein said microprocessor arrangement calculates a time window as one of said parameter ranges wherein, if no request to administer said physiological stimulation using said second stimulation algorithm occurs within said time window, said microprocessor arrangement controls said stimulation administration arrangement to administer said physiological stimulation according to said first stimulation algorithm.

8. An implantable cardiac stimulation device as claimed in claim 1, wherein said microprocessor arrangement comprises a single microprocessor for executing both of said first stimulation algorithm and said second stimulation algorithm.

9. An implantable cardiac stimulation device as claimed in claim 1, wherein said microprocessor arrangement comprises a first microprocessor which executes said first stimulation algorithm and a second microprocessor which executes said second stimulation algorithm.

10. An implantable cardiac stimulation device as claimed in claim 9, wherein said first stimulation algorithm includes a parameter checking algorithm, and wherein said second stimulation algorithm supplies said further stimulation parameters to said stimulation administration arrangement through a filter controlled by said parameter checking algorithm.

11. An implantable cardiac stimulation device as claimed in claim 9, further comprising at least one additional microprocessor for executing at least one additional stimulation algorithm stored in said memory arrangement.