Processing multiply-accumulate operations in a single cycle

• US 6,611,856 B1
• Filed: 12/23/1999
• Issued: 08/26/2003
• Est. Priority Date: 12/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Roberts, David B., Liao, Yuyun, Hameenanttila, Tom M.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/470,836
• Time in Patent Office: 1,342 Days
• Field of Search: 708/620, 708/625, 708/603, 708/501, 708/523
• US Class Current: 708/523
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry look-ahead adder functions simultaneously for different operations.

Claims

1. An apparatus, comprising:

a structure to perform multiple addition operations on a first operand and a second operand;

an adder; and

a controller to permit a first operation to be performed on a portion of the first operand using the structure while the adder is to perform a second operation on another portion of the first operand, wherein the controller is to permit the first operation and the second operation based on whether a plurality of most significant bits of the second operand are identical.

2. The apparatus of claim 1, further comprising an internal storage medium coupled to the adder.

3. The apparatus of claim 2, wherein the internal storage medium comprises one or more accumulators.

4. The apparatus of claim 3, wherein one or more accumulators are coupled to the output of the adder.

5. The apparatus of claim 1, wherein the structure comprises a Wallace tree.

6. The apparatus of claim 5, wherein the Wallace tree comprises a plurality of carry-save adders.

7. The apparatus of claim 6, wherein the Wallace tree is a four-stage Wallace tree.

8. The apparatus of claim 6, wherein the Wallace tree receives nine input vectors and produces two output vectors.

9. The apparatus of claim 1, wherein the adder is a carry look-ahead adder.

10. The apparatus of claim 1, further comprising a Booth encoder coupled to the structure.

11. An apparatus comprising:

a structure to perform multiple addition operations on sets of operand pairs to obtain first results;

an adder; and

a controller to permit a first operation to be performed on a second of the sets of operand pairs using the structure while the adder is to perform a second operation on the first results of a first of the sets of operand pairs, based on whether a plurality of most significant bits of at least one of the first of the sets of operand pairs is identical.

12. The apparatus of claim 11, wherein the structure comprises a Wallace tree.

13. The apparatus of claim 11, wherein the adder comprises a carry look-ahead adder.

14. The apparatus of claim 11, further comprising a Booth encoder coupled to the structure.

15. The apparatus of claim 11, wherein one or more accumulators are coupled to an output of the adder.