Data storage system having separate data transfer section and message network with trace buffer

• US 6,611,879 B1
• Filed: 04/28/2000
• Issued: 08/26/2003
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Dobecki, Krzysztof
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Farooq, Mohammad O.
• Application Number:
  US09/561,161
• Time in Patent Office: 1,215 Days
• Field of Search: 710/1, 710/4, 710/7, 710/20, 710/21, 710/33, 710/36, 710/46, 710/52
• US Class Current: 710/1
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

Claims

1. A system comprising:

a central processing unit for producing information during each of a sequence of bus cycles;

a system resource;

a bus coupled between the system resource and the central processing unit, such bus having produced thereon the sequence of information produced by the central processing unit;

a trace buffer coupled to the bus, such trace buffer having a memory for storing the sequence of information produced on the bus at each of the sequence of bus cycles, such trace buffer comprising;

a register for storing a digital word, such digital word representing a specific control function;

wherein the memory comprises a buffer memory adapted to stored therein a data portion of the information from the central processing unit;

a trace buffer controller, fed an address and control portion of the information from the central processing unit and responsive to the digital word stored in the register, for indicating to the controller whether data from the central processor should be stored in the buffer memory;

whether storage of the data from the central processing unit should be stopped;

or, whether data from the central processing unit and stored in the buffer memory should be read from such buffer memory by the central processing unit.

2. A system interface comprising:

a plurality of first directors;

a plurality of second directors;

a data transfer section having a cache memory, such cache memory being coupled to the plurality of first and second directors;

a messaging network, operative independently of the data transfer section, coupled to the plurality of first directors and the plurality of second directors; and

wherein the first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors with such data passing through the cache memory in the data transfer section;

wherein each one of the first directors includes;

a data pipe coupled between an input of such one of the first directors and the cache memory;

a microprocessor;

a controller;

a common bus, such bus interconnecting the data pipe, the microprocessor, and the controller; and

wherein

the controller controls the transfer of the messages between the message network and such one of the first directors and the data between the input of such one of the first directors and the cache memory; and

a trace buffer coupled to the common bus, such trace buffer having a trace buffer memory for storing the sequence of information produced on the common bus at each of the sequence of bus cycles.

3. The system interface recited in claim 2 wherein each one of the second directors includes:

a data pipe coupled between an input of such one of the second directors and

the cache memory;

a microprocessor;

a controller;

a common bus, such bus interconnecting the data pipe, the microprocessor, and the controller; and

wherein

the controller controls the transfer of the messages between the message network and such one of the second directors and the data between the input of such one of the second directors and the cache memory; and

a trace buffer coupled to the common bus, such trace buffer having a trace buffer memory for storing the sequence of information produced on the common bus at each of the sequence of bus cycles.

4. The system recited in claim 3 wherein each one of the controllers in the second directors includes a bus arbiter coupled to the common bus for arbitrating access to such common bus.

5. The system recited in claim 2 wherein the messaging network comprises a switch having a plurality of ports, each one of such ports being connected to a corresponding one of the plurality of first directors and the plurality of second directors.

6. The system recited in claim 5 wherein each one of the trace buffers comprises:

a register for storing a digital word, such digital word representing a specific control function;

wherein the trace buffer memory comprises a buffer memory adapted to stored therein a data portion of the information from the central processing unit; and

a trace buffer controller, fed an address and control portion of the information from the central processing unit and responsive to the digital word stored in the register, for indicating to the controller whether data from the central processor should be stored in the buffer memory;

whether storage of the data from the central processing unit should be stopped;

or, whether data from the central processing unit and stored in the buffer memory should be read from such buffer memory by the central processing unit.

7. A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface,. such system interface comprising:

a plurality of first directors coupled to host computer/server;

a plurality of second directors coupled to the bank of disk drives;

a data transfer section having a cache memory, such cache memory being coupled to the plurality of first and second directors;

a messaging network, operative independently of the data transfer section, coupled to the plurality of first directors and the plurality of second directors; and

wherein the first and second directors control data transfer between the host computer and the bank of disk drives in response to messages passing between the first directors and the second directors through the messaging network to facilitate the data transfer between host computer/server and the bank of disk drives with such data passing through the cache memory in the data transfer section;

wherein each one of the first directors includes;

a data pipe coupled between an input of such one of the first directors and the cache memory;

a microprocessor;

a controller;

a common bus, such bus interconnecting the data pipe, the microprocessor, and the controller; and

wherein

the controller controls the transfer of the messages between the message network and such one of the first directors and the data between the input of such one of the first directors and the cache memory; and

a trace buffer coupled to the common bus, such trace buffer having a trace buffer memory for storing the sequence of information produced on the common bus at each of the sequence of bus cycles.

8. The storage system recited in claim 7 wherein each one of the second directors includes:

a data pipe coupled between an input of such one of the second directors and the cache memory;

a microprocessor;

a controller;

a common bus, such bus interconnecting the data pipe, the microprocessor, and the controller; and

wherein

the controller controls the transfer of the messages between the message network and such one of the second directors and the data between the input of such one of the second directors and the cache memory; and

a trace buffer coupled to the common bus, such trace buffer having a trace buffer memory for storing the sequence of information produced on the common bus at each of the sequence of bus cycles.

9. The system recited in claim 8 wherein the messaging network comprises a switch having a plurality of ports, each one of such ports being connected to a corresponding one of the plurality of first directors and the plurality of second directors.

10. The system recited in claim 9 wherein each one of the trace buffers comprises:

a register for storing a digital word, such digital word representing a specific control function;

wherein the trace buffer memory comprises a buffer memory adapted to stored therein a data portion of the information from the central processing unit; and

a trace buffer controller, fed an address and control portion of the information from the central processing unit and responsive to the digital word stored in the register, for indicating to the controller whether data from the central processor should be stored in the buffer memory;

whether storage of the data from the central processing unit should be stopped;

or, whether data from the central processing unit and stored in the buffer memory should be read from such buffer memory by the central processing unit.

11. The system recited in claim 7 wherein the messaging network comprises a switch having a plurality of ports, each one of such ports being connected to a corresponding one of the plurality of first directors and the plurality of second directors.

12. The system recited in claim 11 wherein each one of the trace buffers comprises:

a register for storing a digital word, such digital word representing a specific control function;

wherein the trace buffer memory comprises a buffer memory adapted to stored therein a data portion of the information from the central processing unit; and

a trace buffer controller, fed an address and control portion of the information from the central processing unit and responsive to the digital word stored in the register, for indicating to the controller whether data from the central processor should be stored in the buffer memory;

whether storage of the data from the central processing unit should be stopped;

or, whether data from the central processing unit and stored in the buffer memory should be read from such buffer memory by the central processing unit.