Microprocessor architecture capable of supporting multiple heterogeneous processors

• US 6,611,908 B2
• Filed: 06/21/2001
• Issued: 08/26/2003
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Lau, Te-Li, Lentz, Derek J., Hagiwara, Yasuaki, Tang, Cheng-Long, Nguyen, Le Trong
• Primary Examiner(s): Dinh, Dung C.
• Application Number:
  US09/884,943
• Publication Number:
  US 20020059508A1
• Time in Patent Office: 796 Days
• Field of Search: 712/1, 712/28, 712/29, 712/30, 712/32, 712/33, 712/38, 710/240, 710/241, 710/242, 710/243, 710/249, 710/316, 710/317
• US Class Current: 712/29
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Claims

1. A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor, the memory control unit comprising:

a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor;

a switch arbitration unit to arbitrate for access by the one or more devices to said switch network; and

a port arbitration unit to arbitrate for access by the one or more devices to one of the one or more memory ports.

2. The memory control unit of claim 1, wherein the one or more devices comprise one or more of a data cache, an instruction cache, and an input/output unit.

3. The memory control unit of claim 2, wherein the port arbitration unit dynamically allocates priority to one of the one or more devices as a function of an intrinsic priority assigned to each device, the existence of a row match between a requested address and the address of a previously serviced request, the number of times a device has been denied service, and the number of times a device has been serviced without an interruption.

4. The memory control unit of claim 2, wherein the switch arbitration unit gives priority first to requests for the memory ports and then to requests for the input/output unit in a round robin fashion.

5. The memory control unit of claim 2, wherein the switch arbitration unit gives priority to the input/output unit and then to the data cache and instruction cache.

6. The memory control unit of claim 1, further comprising:

a first signal line to transfer, to said port arbitration unit, a request to transfer data between one of the devices and the memory array unit via one of the memory ports;

a second signal line to transfer a port available signal from an available one of the memory ports to said switch arbitration unit when the available port is available to process the request; and

a third signal line responsive to the port available signal to transfer a switch available signal from said switch arbitration unit to said port arbitration unit when said switch network is free to process said request.

7. The memory control unit of claim 1, wherein the one or more memory ports are coupled to the memory array unit by a system bus.

8. In a system including a processor and a memory array unit, wherein the processor includes one or more devices and one or more memory ports, a method for controlling access by the one or more devices to the memory array unit via the one or more memory ports, the method comprising:

transferring data between the one or more devices and the one or more memory ports via a switch network;

arbitrating for access by the one or more devices to said switch network; and

arbitrating for access by the one or more devices to one of the one or more memory ports.

9. The method of claim 8, wherein the one or more devices comprise one or more of a data cache, an instruction cache, and an input/output unit, and wherein said transferring comprises transferring data between the at least one of the one or more memory ports via said switch network and the at least one of the data cache, the instruction cache, and the input/output unit.

10. The method of claim 8, wherein said arbitrating for the one or more memory ports comprises dynamically allocating priority to one of the one or more devices as a function of an intrinsic priority assigned to each device, the existence of a row match between a requested address and the address of a previously serviced request, the number of times a device has been denied service, and the number of times a device has been serviced without an interruption.

11. The method of claim 8, wherein said arbitrating for said switch network comprises giving priority first to the one or more memory ports and then to the input/output unit in a round robin fashion.

12. The method of claim 8, wherein said arbitrating for said switch network comprises giving priority to the input/output unit and then to the data cache and instruction cache.