Method for making projected contact structures for engaging bumped semiconductor devices

• US 6,613,662 B2
• Filed: 08/23/2001
• Issued: 09/02/2003
• Est. Priority Date: 03/26/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wark, James M., Akram, Salman
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, GRANVILL D
• Application Number:
  US09/935,494
• Publication Number:
  US 20010054771A1
• Time in Patent Office: 740 Days
• Field of Search: 438/106, 438/613, 438/25-26, 438/51, 438/64, 438/108, 438/578, 257/678-87, 257/737-38, 257/778-80
• US Class Current: 438/613
• CPC Class Codes: G01R 1/06738 related to tip portion
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump
• CPC Class Codes: H05K 2201/0373 : Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/325 : by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: Y10T 29/49147 : Assembling terminal to base
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base

Abstract

A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are arranged to make electrical contact with the solder balls of a bumped IC device without substantially deforming the solder ball. Accordingly, reflow of solder balls to reform the solder balls is not necessary with the contact pad of the present invention. Such a contact pad may be provided on various testing equipment such as probes and the like and may be used for both temporary and permanent connections. Also disclosed is an improved method of forming the contact pads by etching and deposition.

Claims

1. A method of making at least one projection body for engaging bumped semiconductor devices, said method comprising:

providing a carrier substrate;

forming at least one masking block on said carrier substrate;

etching said carrier substrate to form at least one projection body thereon;

forming a second mask over said at least one projection body, said second mask being shorter and narrower than said at least one masking block; and

etching said carrier substrate to further define said at least one projection body.

2. The method according to claim 1, wherein said providing a carrier substrate comprises providing said carrier substrate having a coefficient of thermal expansion matching a coefficient of thermal expansion of an underlying silicon die.

3. The method according to claim 2, wherein said providing a carrier substrate comprises providing said carrier substrate selected from the group consisting of monocrystalline silicon, silicon-on-glass, silicon-on sapphire, germanium and ceramic.

4. The method according to claim 1, wherein said forming at least one masking block comprises:

forming at least one mask on said carrier substrate; and

patterning and etching said at least one mask selective to said carrier substrate to form a hard mask including said at least one masking block patterned to define a location for said at least one projection body.

5. The method according to claim 4, wherein said patterning and etching comprises etching with phosphoric acid.

6. The method according to claim 4, wherein said forming at least one mask comprises placing a silicon nitride mask on said carrier substrate.

7. The method according to claim 6, wherein said placing a silicon nitride mask comprises depositing said silicon nitride mask by chemical vapor deposition.

8. The method according to claim 6, wherein said forming at least one mask comprises forming a first mask having a thickness of about 500 Å

to 6000 Å

.

9. The method according to claim 1, wherein said etching comprises undercutting said at least one masking block or said second mask with an etchant that reacts with said carrier substrate.

10. The method according to claim 9, wherein said etchant comprises a mixture of KOH and H₂O.

11. The method according to claim 1, wherein said carrier substrate comprises monocrystalline silicon, and said etching said carrier substrate to form at least one projection body comprises forming triangular cross-section, sharp projections.

12. The method according to claim 11, wherein said etching comprises etching a top surface of said carrier substrate faster than sidewalls of said at least one projection body.

13. The method according to claim 12, wherein said etching said carrier substrate comprises defining said sidewalls of said at least one projection body at an angle approximately 54°

relative to a plane defined by said top surface of said carrier substrate.

14. The method according to claim 1, wherein said etching said carrier substrate comprises defining a flat-topped, slope-walled, elongated projection body.

15. The method according to claim 1, wherein said etching said carrier substrate comprises defining a truncated, pyramidal projection body.

16. The method according to claim 1, wherein said etching said carrier substrate comprises forming a closely-spaced array of projection bodies wherein no planar carrier substrate surface extends between adjacent projection bodies.

17. The method according to claim 1, further comprising forming an insulating layer over said at least one projection body and said carrier substrate.

18. The method according to claim 17, wherein said forming an insulating layer comprises exposing said carrier substrate to an oxidizing atmosphere.

19. The method according to claim 17, wherein said forming an insulating layer comprises depositing said insulating layer by chemical vapor deposition.

20. The method according to claim 17, further comprising forming a conductive layer over said insulating layer.

21. The method according to claim 20, wherein said forming a conductive layer comprises forming said conductive layer of metal, said metal selected from the group consisting of aluminum (Al), iridium (Ir), copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), beryllium (Be) and alloys thereof.

22. The method according to claim 20, wherein said forming a conductive layer comprises forming a non-metallic conductive layer.

23. The method according to claim 22, wherein said forming a conductive layer comprises forming said conductive layer of phosphorous-doped polysilicon by LPCVD.

24. The method according to claim 1, where in said at least one projection body extends upwardly from a contact area on said carrier substrate and further comprising forming conductive traces extending from said contact area.

25. The method according to claim 24, wherein said forming conductive traces comprises one of depositing a metal conductor and photopatterning and etching a metal layer.

26. The method according to claim 1, wherein said etching said carrier substrate to form at least one projection body comprises creating said at least one projection body having a point at a narrow end of said at least one masking block and wherein said at least one masking block covers a flat mesa top on the at least one projection body.

27. The method according to claim 26, wherein said etching said carrier substrate to further define said at least one projection body comprises increasing the relative height of said at least one projection body and sharpening said point of said at least one projection body.

28. The method according to claim 1, further comprising sharpening a point of said at least one projection body, said sharpening comprising:

forming a third mask over said at least one projection body, said third mask being shorter and narrower than said at least one masking block and said second mask; and

etching said carrier substrate to sharpen the point of said at least one projection body.

29. The method according to claim 1, wherein said forming at least one masking block comprises forming an elongated trapezoidal, substantially triangular mask or a rectangular mask on said carrier substrate.

30. The method according to claim 1, wherein said etching creates a sloping knife-edge extending longitudinally along substantially an entire length of said at least one projection body defining said at least one projection body, said knife-edge beginning at a surface of said carrier substrate at a narrow end of said at least one projection body.

31. The method according to claim 1, wherein a first projection body of said at least one projection body and a second projection body of said at least one projection body are different relative heights.

32. The method according to claim 1, wherein said etching comprises isotropically etching with a mixture of HF, HNO₃ and H₂O.

33. The method according to claim 32, further comprising forming said at least one projection body to include arcuate and concave sidewalls.

34. The method according to claim 33, further comprising controlling a radius of arc of said sidewalls by varying etch parameters.

35. The method according to claim 1, further comprising:

forming a third mask on said carrier substrate after said etching said carrier substrate to form said at least one projection body thereon, said third mask adjacent said at least one projection body; and

etching said carrier substrate, thereby revealing a second projection body and defining said at least one projection body.

36. The method according to claim 1, wherein said etching comprises exposing said carrier substrate and said at least one projection body to an oxidizing atmosphere.

37. The method according to claim 36, wherein said exposing said carrier substrate and said at least one projection body to an oxidizing atmosphere comprises exposing said carrier substrate and said at least one projection body to steam and O₂ at a temperature of approximately 950°

C.

38. The method according to claim 36, wherein said exposing said carrier substrate and said at least one projection body to an oxidizing atmosphere comprises:

undercutting said at least one projection body beneath said at least one masking block or said second mask; and

forming an oxide layer on exposed portions of said carrier substrate.

39. The method according to claim 38, further comprising removing said oxide layer from said carrier substrate.

40. The method according to claim 39, wherein said removing said oxide layer comprises exposing said carrier substrate to a wet etchant.

41. A method of making at least one contact structure for engaging bumped semiconductor devices, said method comprising:

providing a carrier substrate;

forming contact areas on said carrier substrate, said contact areas including masking blocks;

undercutting said masking blocks to form at least one contact structure;

forming a second mask over said at least one contact structure, said second mask being shorter and narrower than said at least one contact structure; and

undercutting said carrier substrate to further define said at least one contact structure.

42. The method according to claim 41, wherein said providing a carrier substrate comprises providing said carrier substrate having a coefficient of thermal expansion matching a coefficient of thermal expansion of an underlying silicon die.

43. The method according to claim 41, wherein said providing a carrier substrate comprises providing said carrier substrate selected from the group consisting of monocrystalline silicon, silicon-on-glass, silicon-on sapphire, germanium and ceramic.

44. The method according to claim 41, wherein said forming contact areas comprises:

forming at least one mask on said carrier substrate; and

patterning and etching said at least one mask selective to the carrier substrate to form a hard mask including said masking blocks patterned to define said contact areas.

45. The method according to claim 44, wherein said forming at least one mask comprises placing a silicon nitride mask on said carrier substrate.

46. The method according to claim 45, wherein said placing a silicon nitride mask comprises depositing said silicon nitride mask by chemical vapor deposition.

47. The method according to claim 44, wherein said forming at least one mask comprises forming a first mask having a thickness of about 500 Å

to 6000 Å

.

48. The method according to claim 44, wherein said patterning and etching comprises etching with phosphoric acid.

49. The method according to claim 41, wherein said undercutting comprises etching with a mixture of KOH and H₂O.

50. The method according to claim 41, wherein said carrier substrate comprises monocrystalline silicon, and said undercutting comprises forming triangular cross-section, sharp projections.

51. The method according to claim 50, wherein said undercutting comprises etching a top surface of said carrier substrate faster than sidewalls of said at least one contact structure.

52. The method according to claim 51, wherein said undercutting comprises creating said sidewalls of said at least one contact structure at an angle approximately 54°

relative to a plane defined by said top surface of said carrier substrate.

53. The method according to claim 41, wherein said undercutting comprises forming a flat-topped, slope-walled, elongated contact structure.

54. The method according to claim 41, wherein said undercutting comprises forming a truncated, pyramidal contact structure.

55. The method according to claim 41, wherein said undercutting comprises forming a closely-spaced array of contact structures wherein no planar carrier substrate surface extends between adjacent contact structures.

56. The method according to claim 41, further comprising forming an insulating layer over said at least one contact structure and said carrier substrate.

57. The method according to claim 56, wherein said forming an insulating layer comprises exposing said carrier substrate to an oxidizing atmosphere.

58. The method according to claim 56, wherein said forming an insulating layer comprises depositing said insulating layer by chemical vapor deposition.

59. The method according to claim 56, further comprising forming a conductive layer over said insulating layer.

60. The method according to claim 59, wherein said forming a conductive layer comprises forming said conductive layer of metal, said metal selected from the group consisting of aluminum (Al), iridium (Ir), copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), beryllium (Be) and alloys thereof.

61. The method according to claim 59, wherein said forming a conductive layer comprises forming a non-metallic conductive layer.

62. The method according to claim 61, wherein said forming a conductive layer comprises forming said conductive layer of phosphorous-doped polysilicon by LPCVD.

63. The method according to claim 41, further comprising forming conductive traces extending from said contact areas.

64. The method according to claim 63, wherein said forming conductive traces comprises one of depositing a metal conductor and photopatterning and etching a metal layer.

65. The method according to claim 41, wherein said undercutting said masking blocks comprises creating said at least one contact structure having a point at a narrow end of said masking blocks and wherein said masking blocks covers a flat mesa top on the at least one contact structure.

66. The method according to claim 65, wherein said undercutting said carrier substrate comprises increasing the relative height of said at least one contact structure and sharpening said point of said at least one contact structure.

67. The method according to claim 41, further comprising sharpening a point of said at least one contact structure, said sharpening comprising:

forming a third mask over said at least one contact structure, said third mask being shorter and narrower than said masking blocks and said second mask; and

etching said carrier substrate to sharpen the point of said at least one contact structure.

68. The method according to claim 41, wherein said forming said second mask comprises forming an elongated trapezoidal, substantially triangular mask or a rectangular mask.

69. The method according to claim 41, wherein said undercutting comprises forming a sloping knife-edge extending longitudinally along substantially an entire length of said at least one contact structure to define said at least one contact structure, said knife-edge beginning at a surface of said carrier substrate at a narrow end of said at least one contact structure.

70. The method according to claim 41, wherein a first contact structure of said at least one contact structure and a second contact structure of said at least one contact structure are different relative heights.

71. The method according to claim 41, wherein said undercutting comprises isotropically etching with a mixture of HF, HNO₃ and H₂O.

72. The method according to claim 71, further comprising forming said at least one contact structure to include arcuate and concave sidewalls.

73. The method according to claim 72, further comprising controlling a radius of arc of said sidewalls by varying etch parameters.

74. The method according to claim 41, further comprising:

forming a third mask on said carrier substrate after said undercutting said masking blocks to form said at least one contact structure thereon, said third mask adjacent said at least one contact structure; and

undercutting said carrier substrate, thereby revealing a second contact structure and further defining said at least one contact structure.

75. The method according to claim 41, wherein said undercutting comprises exposing said carrier substrate and said at least one contact structure to an oxidizing atmosphere.

76. The method according to claim 75, wherein said exposing said carrier substrate and said at least one contact structure to an oxidizing atmosphere comprises exposing said carrier substrate and said at least one contact structure to steam and O₂ at a temperature of approximately 950°

C.

77. The method according to claim 75, wherein said exposing said carrier substrate and said at least one contact structure to an oxidizing atmosphere comprises:

undercutting said at least one contact structure beneath said masking blocks or said second mask; and

forming an oxide layer on exposed portions of said carrier substrate.

78. The method according to claim 77, further comprising removing said oxide layer from said carrier substrate.

79. The method according to claim 78, wherein said removing said oxide layer comprises exposing said carrier substrate to a wet etchant.

80. A method of forming contact structures for engaging outer surfaces of solder balls without substantially deforming said outer surfaces of the solder balls, said method comprising:

forming a first set of masks on a carrier substrate;

etching said carrier substrate revealing a first set of projection bodies having a first height;

forming a second set of masks adjacent said first set of masks; and

etching said carrier substrate revealing a second set of projection bodies having a second height and defining further said first set of projection bodies.

81. The method according to claim 80, wherein said forming said first set of masks comprises:

forming at least one mask on said carrier substrate; and

patterning and etching said at least one mask selective to the carrier substrate thereby forming a hard mask including said first set of masks patterned to define contact pad locations for said first set of projection bodies.

82. The method according to claim 81, wherein said patterning and etching comprises etching with phosphoric acid.

83. The method according to claim 81, wherein said forming at least one mask comprises placing a silicon nitride mask on said carrier substrate.

84. The method according to claim 83, wherein said placing a silicon nitride mask comprises depositing said silicon nitride mask by chemical vapor deposition.

85. The method according to claim 83, wherein said forming at least one mask comprises forming a first mask having a thickness of about 500 Å

to 6000 Å

.

86. The method according to claim 80, wherein said etching comprises undercutting said first set of masks and said second set of masks with an etchant that reacts with said carrier substrate.

87. The method according to claim 86, wherein said etchant comprises a mixture of KOH and H₂O.

88. The method according to claim 80, wherein said carrier substrate comprises monocrystalline silicon, and said etching said carrier substrate to reveal said first set of projection bodies comprises forming triangular cross-section, sharp projections.

89. The method according to claim 88, wherein a top surface of said carrier substrate etches faster than sidewalls of each projection body of said first set of projection bodies.

90. The method according to claim 89, wherein said etching said carrier substrate revealing said first set of projection bodies comprises creating said sidewalls of each said projection body of said first set of projection bodies at an angle approximately 54°

relative to a plane defined by said top surface of said carrier substrate.

91. The method according to claim 80, wherein said etching said carrier substrate revealing said first set of projection bodies comprises forming a flat-topped, slope-walled, elongated projection body.

92. The method according to claim 80, wherein said etching said carrier substrate revealing said first set of projection bodies comprises forming a truncated, pyramidal projection body.

93. The method according to claim 80, wherein said etching said carrier substrate revealing said first set of projection bodies comprises forming a closely-spaced array of projection bodies wherein no planar carrier substrate surface extends between adjacent projection bodies.

94. The method according to claim 80, further comprising forming an insulating layer over said first set of projection bodies, said second set of projection bodies and said carrier substrate.

95. The method according to claim 94, wherein said forming an insulating layer comprises exposing said carrier substrate to an oxidizing atmosphere.

96. The method according to claim 94, wherein said forming an insulating layer comprises depositing said insulating layer by chemical vapor deposition.

97. The method according to claim 94, further comprising forming a conductive layer over said insulating layer.

98. The method according to claim 97, wherein said forming a conductive layer comprises forming said conductive layer of metal, said metal selected from the group consisting of aluminum (Al), iridium (Ir), copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), beryllium (Be) and alloys thereof.

99. The method according to claim 98, wherein said forming a conductive layer comprises forming a non-metallic conductive layer.

100. The method according to claim 99, wherein said forming a conductive layer comprises forming said conductive layer of phosphorous-doped polysilicon by LPCVD.

101. The method according to claim 80, wherein each projection body of said first set of projection bodies extends upwardly from a contact area on said carrier substrate and further comprising forming conductive traces extending from said contact area.

102. The method according to claim 101, wherein said forming conductive traces comprises one of depositing a metal conductor and photopatterning and etching a metal layer.

103. The method according to claim 80, wherein said etching said carrier substrate revealing said first set of projection bodies comprises creating a first projection body of said first set of projection bodies having a point at a narrow end of a first mask of said first set of masks and wherein said first mask covers a flat mesa top on the first projection body.

104. The method according to claim 103, wherein said etching said carrier substrate revealing a second set of projection bodies having a second height and defining further said first set of projection bodies comprises increasing the relative height of said first set of projection bodies and sharpening said point of said first projection body.

105. The method according to claim 80, further comprising sharpening a point of said first set of projection bodies and said second set of projection bodies, said sharpening comprising:

forming a first mask over each projection body of said first set of projection bodies, said first mask being shorter and narrower than said first set of masks;

forming a second mask over each projection body of said second set of projection bodies, said second mask being shorter and narrower than said second set of masks; and

etching said carrier substrate, thereby sharpening the point of each said projection body of said first set of projection bodies and each said projection body of said second set of projection bodies.

106. The method according to claim 80, wherein said forming a first set of masks comprises forming an elongated trapezoidal, substantially triangular mask or a rectangular mask on said carrier substrate.

107. The method according to claim 80, wherein said etching comprises creating a sloping knife-edge extending longitudinally along substantially an entire length of a first projection body of said first set of projection bodies, defining said first projection body, said knife-edge beginning at a surface of said carrier substrate at a narrow end of said first projection body.

108. The method according to claim 80, wherein said first set of projection bodies are relatively taller than said second set of projection bodies.

109. The method according to claim 80, wherein said etching comprises isotropically etching with a mixture of HF, HNO₃ and H₂O.

110. The method according to claim 109, further comprising forming said first set of projection bodies and said second set of projection bodies to include arcuate and concave sidewalls.

111. The method according to claim 110, further comprising controlling a radius of arc of said sidewalls by varying etch parameters.

112. The method according to claim 80, further comprising:

forming a third set of masks adjacent said second set of masks; and

etching said carrier substrate revealing a third set of projection bodies having a third height and increasing a relative height of said first set of projection bodies and said second set of projection bodies.

113. The method according to claim 80, wherein said first set of masks comprises interior windows and said etching comprises anistropically etching said carrier substrate forming facing sloped walls on said interior windows.

114. The method according to claim 113, further comprising:

masking said interior windows; and

etching isotropically about the periphery of the interior windows.

115. The method according to claim 80, further comprising configuring said first set of projection bodies in a concentric, radially extending and symmetrical pattern.

116. The method according to claim 80, further comprising configuring said second set of projection bodies in a concentric, radially extending and symmetrical pattern.

117. The method according to claim 80, wherein said etching comprises exposing said carrier substrate to an oxidizing atmosphere.

118. The method according to claim 117, wherein said exposing said carrier substrate to an oxidizing atmosphere comprises exposing said carrier substrate to steam and O₂ at a temperature of approximately 950°

C.

119. The method according to claim 118, wherein said exposing said carrier substrate to an oxidizing atmosphere comprises:

undercutting said first set of projection bodies beneath said first set of masks; and

forming an oxide layer on exposed portions of said carrier substrate.

120. The method according to claim 119, further comprising removing said oxide layer from said carrier substrate.

121. The method according to claim 120, wherein said removing said oxide layer comprises exposing said carrier substrate to a wet etchant.