Conductive line formed on integrated circuits

• US 6,614,114 B2
• Filed: 05/25/2001
• Issued: 09/02/2003
• Est. Priority Date: 02/10/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Gris, Yvon
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US09/865,634
• Publication Number:
  US 20010036734A1
• Time in Patent Office: 830 Days
• Field of Search: 257/775, 257/758, 257/762, 257/765, 257/774
• US Class Current: 257/750
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213

Abstract

The present invention relates to a conductive line on an integrated circuit. The integrated circuit includes an insulating layer in which is formed several grooves of predetermined width. The conductive line includes a first interconnection layer having a first thickness and a second interconnection layer having a second thickness. The predetermined width is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.

Claims

1. A conductive line formed on a surface of a substrate, the upper surface of the substrate comprising an insulating layer in which is formed several parallel grooves of predetermined width, the conductive line including:

a first interconnection layer of a first thickness; and

a second interconnection layer of a second thickness, the predetermined width being greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thickness.

2. The conductive line of claim 1, wherein the several parallel grooves are distanced from one another by portions of the insulating layer and wherein said portions of the insulating layer have a width that is small in comparison to the predetermined width of each of the grooves.

3. An integrated circuit comprising:

an insulating layer in which are formed several grooves that are each distanced from one another and of predetermined width; and

a conductive line comprising;

a first interconnection layer disposed over the insulating layer, portions of the first interconnection layer extending into each of the grooves such that the portions of the first connection layer are electrically connected together, the first interconnection layer having a first thickness, and

a second interconnection layer disposed over the first interconnection layer and electrically connected to the first interconnection layer, the second interconnection layer having a second thickness;

wherein the predetermined width of each of the grooves is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.

4. The integrated circuit of claim 3 wherein the first interconnection layer defines several channels each overlying a respective one of the grooves.

5. The integrated circuit of claim 4 wherein each channel is of a width that is less than the predetermined width of the respective groove.

6. The integrated circuit of claim 5 wherein the width of each channel is substantially equal to the predetermined width of the respective groove less twice the first thickness.

7. The integrated circuit of claim 5 wherein the grooves are distanced from one another by portions of the insulating layer.

8. The integrated circuit of claim 7 wherein said portions of the insulating layer have a width that is small in comparison to the predetermined width of each of the grooves.

9. The integrated circuit of claim 8 wherein the second interconnection layer fills the channels.

10. The integrated circuit of claim 9, wherein the second thickness is greater than one half the width of the channels.

11. The integrated circuit of claim 9, wherein the several grooves are parallel to one another.

12. The integrated circuit claim 11 wherein the thickness of the insulating layer is on the order of 0.6 to 0.8 μ

m, the predetermined width of each of the grooves is on the order of 2 to 4 μ

m and the width of said portions of the insulator layer is on the order of 0.4 μ

m.

13. The integrated circuit of claim 12 wherein the first interconnection layer is made of aluminum or aluminum-copper and is of a thickness t1 between 0.6 and 1 μ

m, and the second interconnection layer is made of aluminum or aluminum-copper and is of a thickness on the order of 0.8 to 1.2 μ

m.

14. The integrated circuit of claim 9 further comprising conductive spacers of a third thickness on lateral walls of each of the grooves.

15. The integrated circuit of claim 14 wherein the predetermined width of each of the grooves is smaller than twice the sum of the first, second, and third thicknesses.

16. The integrated circuit of claim 15, wherein the several grooves are parallel to one another.

17. The integrated circuit of claim 3, wherein the several grooves are parallel to one another.

18. The integrated circuit of claim 3 wherein the grooves are distanced from one another by portions of the insulating layer.

19. The integrated circuit of claim 18 wherein said portions of the insulating layer have a width that is small in comparison to the predetermined width of each of the grooves.

20. The integrated circuit of claim 19 wherein the thickness of the insulating layer is on the order of 0.6 to 0.8 μ

m, the predetermined width of each of the grooves is on the order of 2 to 4 μ

m and the width of said portions of the insulator layer is on the order of 0.4 μ

m.

21. The integrated circuit of claim 20 wherein the first interconnection layer is made of aluminum or aluminum-copper and is of a thickness t1 between 0.6 and 1 μ

m, and the second interconnection layer is made of aluminum or aluminum-copper and is of a thickness on the order of 0.8 to 1.2 μ

m.

22. The integrated circuit of claim 3 further comprising conductive spacers of a third thickness on lateral walls of each of the grooves.

23. The integrated circuit of claim 22 wherein the predetermined width of each of the grooves is smaller than twice the sum of the first, second, and third thicknesses.

24. The integrated circuit of claim 4, wherein the second thickness is greater than one half the width of the channels.

25. The integrated circuit of claim 4 wherein the second interconnection layer fills the channels.

26. The integrated circuit of claim 25 wherein the second interconnection layer is comprised of aluminum and copper.

27. The integrated circuit of claim 3 wherein the integrated circuit has at least one operating state in which the conductive line conducts current.

28. The integrated circuit of claim 27 wherein the first interconnection layer defines several channels each overlying a respective one of the grooves.

29. The integrated circuit of claim 28 wherein each channel is of a width that is less than the predetermined width of the respective groove.

30. The integrated circuit of claim 29 wherein the width of each channel is substantially equal to the predetermined width of the respective groove less twice the first thickness.

31. The integrated circuit of claim 29 wherein the grooves are distanced from one another by portions of the insulating layer.

32. The integrated circuit of claim 31 wherein said portions of the insulating layer have a width that is small in comparison to the predetermined width of each of the grooves.

33. The integrated circuit of claim 32 wherein the second interconnection layer fills the channels.

34. The integrated circuit of claim 33, wherein the second thickness is greater than one half the width of the channels.

35. The integrated circuit of claim 33, wherein the several grooves are parallel to one another.

36. The integrated circuit of claim 35 wherein the thickness of the insulating layer is on the order of 0.6 to 0.8 μ

m, the predetermined width of each of the grooves is on the order of 2 to 4 μ

m and the width of said portions of the insulator layer is on the order of 0.4 μ

m.

37. The integrated circuit of claim 36 wherein the first interconnection layer is made of aluminun or aluminum-copper and is of a thickness of t1 between 0.6 and 1 μ

m, and the second interconnection layer is made of aluminum or aluminum-copper and is of a thickness on the order of 0.8 to 1.2 μ

m.

38. The integrated circuit of claim 33 further comprising conductive spacers of a third thickness on lateral walls of each of the grooves.

39. The integrated circuit of claim 38 wherein the predetermined width of each of the grooves is smaller than twice the sum of the first, second, and third thicknesses.