Logic architecture for single event upset immunity

• US 6,614,257 B2
• Filed: 05/11/2001
• Issued: 09/02/2003
• Est. Priority Date: 05/12/2000
• Status: Expired due to Fees

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Knowles, Kenneth R.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/854,247
• Publication Number:
  US 20020017924A1
• Time in Patent Office: 844 Days
• Field of Search: 326/9, 326/13, 326/27, 326/119, 257/369, 257/371, 257/379, 257/380, 365/72, 365/156, 365/181, 365/53, 365/190
• US Class Current: 326/9
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/0075 by using two redundant chains

Abstract

An SEU immune logic architecture includes a dual path logic gate coupled to a dual to single path converter. A first and a second logic element within the dual path logic gate are functionally and possibly structurally equivalent, and are coupled to receive input signals spanning redundant input signal sets. A given logic structure within the first logic element may receive specified input signals within a particular input signal set, while an analogous logic structure within the second logic element may receive corresponding input signals within the counterpart input signal set. A radiation induced transient pulse that affects one input signal may affect an output signal asserted by one logic structure; however, since the transient pulse doesn'"'"'t affect a corresponding input signal applied to the analogous logic structure, the dual path logic gate may output at least one correctly valued signal when a transient pulse occurs. The dual to single path converter is coupled to receive signals output by the dual path logic gate. In the event that a transient signal appears at an input of the dual to single path converter, a current path may be interrupted, and a correct output signal value is maintained as a result of stray capacitance present at an output node.

Claims

1. A logic circuit comprising:

a first logic circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second logic circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second logic circuit logically equivalent to the first logic circuit; and

a conversion circuit having an output, a first input coupled to the output of the first logic circuit, and a second input coupled to the output of the second logic circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

2. The logic circuit of claim 1, wherein the second logic circuit is architecturally equivalent to the first logic circuit.

3. The logic circuit of claim 1, wherein the first logic circuit comprises an inverter.

4. The logic circuit of claim 1, wherein the first logic circuit comprises a CMOS inverter.

5. The logic circuit of claim 1, wherein the first logic circuit comprises a NAND gate.

6. The logic circuit of claim 1, wherein the first logic circuit comprises a CMOS NAND gate.

7. The logic circuit of claim 1, wherein the first logic circuit comprises a NOR gate.

8. The logic circuit of claim 1, wherein the first logic circuit comprises a CMOS NOR gate.

9. The logic circuit of claim 1, wherein the first inverter circuit is coupled to the output of the first logic circuit and the second inverter circuit is coupled to the output of the second logic circuit.

10. The logic circuit of claim 1, wherein the first inverter circuit is coupled to the output of the first logic circuit and the second inverter circuit is coupled to the output of the second logic circuit, and the first inverter circuit has an output that forms an output of the conversion circuit.

11. A circuit comprising:

a first inverter circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second inverter circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal; and

a conversion circuit having an output, a first input coupled to the output of the first inverter circuit, and a second input coupled to the output of the second inverter circuit, the conversion circuit comprising a third inverter circuit that forms a portion of a current path within a fourth inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

12. A circuit comprising:

a first inverter circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal;

a second inverter circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal;

a third inverter circuit having an output, a first input coupled to receive a first version of a signal output by the first inverter circuit, and a second input coupled to receive a second version of a signal output by the second inverter circuit;

a fourth inverter circuit having an output, a first input coupled to receive a second version of a signal output by the first inverter circuit, and a second input coupled to receive a first version of a signal output by the second inverter circuit; and

a conversion circuit having an output, a first input coupled to the output of the third inverter circuit, and a second input coupled to the output of the fourth inverter circuit, the conversion circuit comprising a fifth inverter circuit that forms a portion of a current path within a sixth inverter circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse, the first and second versions of the signal output by the first inverter circuit correspond to an identical value in the absence of a transient pulse, and the first and second versions of the signal output by the second inverter circuit correspond to an identical value in the absence of a transient pulse.

13. A circuit comprising:

a first NAND circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal; and

a second NAND circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second NAND circuit logically equivalent to the first NAND circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

14. The circuit of claim 13, further comprising a conversion circuit having an output, a first input coupled to the output of the first NAND circuit, and a second input coupled to the output of the second NAND circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit.

15. A circuit comprising:

a first NOR circuit having an output, a first input coupled to receive a first version of a first input signal, and a second input coupled to receive a second version of a second input signal; and

a second NOR circuit having an output, a first input coupled to receive a second version of the first input signal, and a second input coupled to receive a first version of the second input signal, the second NOR circuit logically equivalent to the first NOR circuit,

wherein the first and second versions of the first input signal correspond to an identical value in the absence of a transient pulse, and the first and second versions of the second input signal correspond to an identical value in the absence of a transient pulse.

16. The circuit of claim 15, further comprising a conversion circuit having an output, a first input coupled to the output of the first NOR circuit, and a second input coupled to the output of the second NOR circuit, the conversion circuit comprising a first inverter circuit that forms a portion of a current path within a second inverter circuit.