Multi-stage, high frequency, high power signal amplifier

• US 6,614,308 B2
• Filed: 10/22/2001
• Issued: 09/02/2003
• Est. Priority Date: 10/22/2001
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Perugupalli, Prasanth, Leighton, Larry, Moller, Thomas W.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHANH V
• Application Number:
  US10/037,638
• Publication Number:
  US 20030076173A1
• Time in Patent Office: 680 Days
• Field of Search: 330/65, 330/66, 330/67, 330/68, 330/286, 330/295, 330/302
• US Class Current: 330/295
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2224/32188 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01072 Hafnium [Hf]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03F 3/604 : using FET's

Abstract

A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal. A plurality of corresponding output matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple the respective component output signals at the transistor outputs to an output impedance.

Claims

1. A broadband radio frequency (RF) signal amplifier, comprising:

a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output, the pedestal comprising a support structure, reference ground and heat sink for the transistors;

a RF input path electrically connected to the transistor inputs, the input path including a splitter configured to split a RF input signal into a plurality of component input signals, a plurality of input matching networks, each input matching network configured to couple a respective component input signal to a respective transistor input at an input impedance, and a plurality of input direct current (dc) bias networks, each input dc bias network configured to bias a respective transistor input to an input operating point, the splitter, input matching networks and input bias networks at least partially implemented in a multi-layer printed circuit board; and

a RF output path electrically connected to the transistor outputs, the output path including a combiner configured to combine component output signals received at the transistor outputs into a RF output signal, a plurality of output matching networks, each output matching network configured to couple a respective component output signal to a respective transistor output at an output impedance, and a plurality of output dc bias networks, each output dc bias network configured to bias a respective transistor output to an output operating point, the combiner, output matching networks and output bias networks at least partially implemented in the printed circuit board;

wherein the pedestal is configured such that when it is positioned with respect to the printed circuit board, an input or output grounding shelf of the printed circuit board is in close proximity with a mounting surface of the pedestal.

2. The amplifier of claim 1, the printed circuit board having an opening sized to accommodate the pedestal.

3. The amplifier of claim 1, the input and output paths comprising respective input and output reference ground shelves implemented in the printed circuit board, the pedestal and printed circuit board arranged such that the input and output reference ground shelves are adjacent the pedestal surface.

4. The amplifier of claim 3, further comprising respective conductors electrically connecting the input and output reference ground shelves to the pedestal surface.

5. The amplifier of claim 4, the conductors comprising respective sets of bond wires, the printed circuit board and pedestal located sufficiently close such that the bond wires provide relatively low inductance transmission paths.

6. The amplifier of claim 1, the input matching networks comprising transmission lines implemented in the printed circuit board and electrically connecting the component input signals to respective transistor inputs, the transmission lines having lengths approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal.

7. The amplifier of claim 1, the output matching networks comprising transmission lines implemented in the printed circuit board and electrically connecting component output signals to the combiner, the transmission lines having lengths approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal.

8. The amplifier of claim 1, the input matching networks comprising respective input matching capacitors attached to the pedestal, the respective input bias networks electrically connecting an input dc bias source to a respective input matching capacitor, the output matching networks comprising respective output matching capacitors attached to the pedestal, the respective output bias networks electrically connecting an output dc bias source to a respective output matching capacitor.

9. The amplifier of claim 8, wherein the input dc bias source is connected to the input matching capacitors via respective input transmission lines implemented in the printed circuit board, and wherein the output dc bias source is connected to the output matching capacitors via respective output transmission lines implemented in the printed circuit board, the respective input and output transmission lines each having a length approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal.

10. The amplifier of claim 8, wherein the input dc bias source is connected to the input matching capacitors, and the output dc bias source is connected to the output matching capacitors, without the either of input or output dc bias source being transmitted via a transmission line having a length approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal.

11. The amplifier of claim 1, wherein the splitter and combiner are passive elements.

12. The amplifier of claim 1, wherein the input impedance is relatively high, and the input operating point is relatively low.

13. The amplifier of claim 1, further comprising

a first plurality of conductors electrically connecting respective input path transmission lines implemented in the printed circuit board to respective transistor inputs, and

a second plurality of conductors electrically connecting respective output path transmission lines implemented in the printed circuit board to respective transistor outputs.

14. The amplifier of claim 12, wherein the first and second pluralities of conductors comprise respective sets of bond wires extending between the printed circuit board and the pedestal.

15. The amplifier of claim 1, wherein the pedestal and printed circuit board are attached to a common reference ground and heat sink.

16. The amplifier of claim 15, the input and output paths comprising respective input and output reference ground shelves implemented in the printed circuit board, the input and output ground shelves electrically connected to the pedestal by respective pluralities of bond wires providing low inductance paths.

17. A broadband radio frequency (RF) signal amplifier, comprising:

a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output, the pedestal comprising a support structure, reference ground and heat sink for the transistors;

a RF input path electrically connected to the transistor inputs, the input path including a splitter configured to split a RF input signal into a plurality of component input signals, a plurality of input matching networks, each input matching network configured to couple a respective component input signal to a respective transistor input at an input impedance, and a plurality of input direct current (dc) bias networks, each input dc bias network configured to bias a respective transistor input to an input operating point, the splitter, input matching networks and input bias networks at least partially implemented in a multi-layer printed circuit board, the input matching networks comprising respective input matching capacitors attached to the pedestal; and

a RF output path electrically connected to the transistor outputs, the output path including a combiner configured to combine component output signals at the transistor outputs into a RF output signal, a plurality of output matching networks, each output matching network configured to couple a respective component output signal to a respective transistor output at an output impedance, and a plurality of output dc bias networks, each output dc bias network configured to bias a respective transistor output to an output operating point, the combiner, output matching networks and output bias networks at least partially implemented in the printed circuit board, the output matching networks comprising respective output matching capacitors attached to the pedestal;

wherein the pedestal is configured such that when it is positioned with respect to the printed circuit board, an input or output grounding shelf of the printed circuit board is in close proximity with a mounting surface of the pedestal.

18. The amplifier of claim 17, the input dc bias networks electrically connecting an input dc bias source to respective input matching capacitors, and the output dc bias networks electrically connecting an output dc bias source to respective output matching capacitors, without the either of input or output dc bias source being transmitted via a transmission line having a length approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal.

19. The amplifier of claim 17, the printed circuit board having an opening sized to accommodate the pedestal.

20. The amplifier of claim 17, the input and output paths comprising respective input and output reference ground shelves implemented in the printed circuit board, the pedestal and printed circuit board arranged such that the input and output reference ground shelves are adjacent the pedestal surface.

21. The amplifier of claim 20, further comprising respective bond wire conductors electrically connecting the input and output reference ground shelves to the pedestal surface, the input and output reference ground shelves and the pedestal surface sufficiently close such that the bond wires provide relatively low inductance transmission paths.

22. A broadband radio frequency (RF) signal amplifier, comprising:

a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output;

a RF input path electrically connected to the transistor inputs, the input path including a splitter configured to split a RF input signal into a plurality of component input signals, and a plurality of input matching networks, each input matching network configured to couple a respective component input signal to a respective transistor input at an input impedance, the splitter and input matching networks at least partially implemented in a multi-layer printed circuit board, the input matching networks comprising respective input matching capacitors attached to the pedestal; and

a RF output path electrically connected to the transistor outputs, the output path including a combiner configured to combine component output signals at the transistor outputs into a RF output signal, and a plurality of output matching networks, each output matching network configured to couple a respective component output signal to a respective transistor output at an output impedance, the combiner and output matching networks at least partially implemented in the printed circuit board, the output matching networks comprising respective output matching capacitors attached to the pedestal;

wherein the pedestal is configured such that when it is positioned with respect to the printed circuit board, an input or output grounding shelf of the printed circuit board is in close proximity with a mounting surface of the pedestal.

23. The amplifier of claim 22, the printed circuit board having an opening sized to accommodate the pedestal.

24. The amplifier of claim 22, the input and output paths comprising respective input and output reference ground shelves implemented in the printed circuit board, the pedestal and printed circuit board arranged such that the input and output reference ground shelves are adjacent the pedestal surface, wherein respective bond wire conductors electrically connect the input and output reference ground shelves to the pedestal surface, the input and output reference ground shelves and the pedestal surface sufficiently close such that the bond wires provide relatively low inductance transmission paths.

25. The amplifier of claim 22, wherein

the input path further comprises a plurality of input bias networks electrically connecting an input direct current (dc) bias source to the input matching capacitors, and

the output path further comprises a plurality of input bias networks electrically connecting an output dc bias source to the output matching capacitors.

26. The amplifier of claim 25, wherein

the input dc bias source is connected to the input matching capacitors through respective transmission lines implemented in the printed circuit board, each having a length approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal, and

the output dc bias source is connected to the output matching capacitors through respective transmission lines implemented in the printed circuit board, each having a length approximating one-fourth of a wavelength of a fundamental frequency of the RF input signal.

27. The amplifier of claim 25, wherein the input dc bias source is connected to the input matching capacitors, and the output dc bias source is connected to the output matching capacitors, without the either of input or output dc bias source being transmitted through a one-fourth wavelength transmission line.