Voltage controlled oscillator with jitter correction

• US 6,614,318 B1
• Filed: 11/05/2001
• Issued: 09/02/2003
• Est. Priority Date: 11/05/2001
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Boecker, Charles W.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Chang, Joseph
• Application Number:
  US10/011,475
• Time in Patent Office: 666 Days
• Field of Search: 331/17, 331/11, 331/10, 331/25
• US Class Current: 331/17
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/02 using a frequency discriminator comprising a passive frequency-determining element
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase controller is coupled to a voltage-controlled oscillator (VCO) in a feedback configuration, thereby reducing the phase noise introduced by the VCO. As a result, circuits using the VCO, such as phase-locked loops or delay locked loops, will exhibit reduced jitter in the resulting output signals. In one embodiment, the phase controller measures successive actual periods of the VCO output clock, and in response, generates a control voltage representative of deviations in the successive actual periods of the VCO output clock. The phase controller transmits the control voltage to the VCO as a feedback control voltage. The VCO adjusts the actual period of the VCO output clock in response to the control voltage. More specifically, the VCO adjusts the actual period of the VCO output clock such that deviations in the successive actual periods of the VCO output clock are reduced.

Claims

1. A method of operating a signal controlled oscillator that provides an output clock having an actual period, the method comprising:

directly measuring successive actual periods of the output clock;

generating a control signal representative of deviations in the successive actual periods of the output clock; and

adjusting the actual period of the output clock in response to the control signal.

2. The method of claim 1, wherein the adjusting reduces the deviations in the successive actual periods of the output clock.

3. The method of claim 1, further comprising selecting a desired period of the output clock, wherein the adjusting forces the actual period of the output clock toward the desired period of the output clock.

4. The method of claim 1, wherein the control signal changes in a linear manner with respect to changes in the actual period.

5. The method of claim 1, wherein the control signal increases as the actual period increases, and decreases as the actual period decreases.

6. The method of claim 1, further comprising:

routing the output clock to a phase comparator;

routing a reference clock signal to the phase comparator;

generating an error signal representative of the difference between the output clock and the reference clock signal; and

controlling the signal controlled oscillator in response to the error signal.

7. A method of operating a signal controlled oscillator that provides an output clock having an actual period, the method comprising:

measuring successive actual periods of the output clock;

generating a control signal representative of deviations in the successive actual periods of the output clock;

filtering the control signal using a high-pass filter; and

adjusting the actual period of the output clock in response to the control signal.

8. A method of operating a signal controlled oscillator that provides an output clock having an actual period, the method comprising:

measuring successive actual periods of the output clock;

generating a control signal representative of deviations in the successive actual periods of the output clock, wherein the control signal is generated by;

generating a first signal having a magnitude corresponding with a first half period of the output clock;

generating a second signal having a magnitude corresponding with a second half period of the output clock; and

generating the control signal in response to the first signal and the second signal; and

adjusting the actual period of the output clock in response to the control signal.

9. The method of claim 8, wherein the first signal is generated by charging a first capacitor during each first half period of the output clock, and discharging the first capacitor to a predetermined level during each second half period of the output clock.

10. The method of claim 9, wherein the second signal is generated by charging a second capacitor during each second half period of the output clock, and discharging the second capacitor to the predetermined level during each first half period of the output clock.

11. The method of claim 8, further comprising generating the control signal charging a capacitor in response to the first and second signals.

12. The method of claim 11, further comprising:

charging the capacitor when the first signal or the second signal exceeds the control signal; and

discharging the capacitor when neither the first signal nor the second signal exceeds the control signal.

13. A signal controlled oscillator comprising:

means for directly measuring successive actual periods of an output clock provided by the signal controlled oscillator;

means for generating a control signal representative of deviations in the successive actual periods of the output clock; and

means for adjusting the actual period of the output clock in response to the control signal.

14. The signal controlled oscillator of claim 13, wherein the means for adjusting reduce the deviations in the successive actual periods of the output clock.

15. The signal controlled oscillator of claim 13, wherein the means for adjusting forces the actual period of the output clock toward a desired period of the output clock.

16. A signal controlled oscillator system comprising:

a signal controlled oscillator configured to generate an output clock having an actual period in response to an input signal;

a phase controller coupled to receive the output clock, the phase controller being configured to generate a control signal directly in response to the output clock, wherein the control signal is representative of cycle-to-cycle deviations in the actual period of the output clock; and

a feedback line for transmitting the control signal to the signal controlled oscillator.

17. A signal controlled oscillator system comprising:

a signal controlled oscillator configured to generate an output clock having an actual period in response to an input signal;

a phase controller coupled to receive the output clock, the chase controller being configured to generate a control signal representative of cycle-to-cycle deviations in the actual period of the output clock; and

a feedback line for transmitting the control signal to the signal controlled oscillator, wherein the signal controlled oscillator includes a circuit for combining the control signal with the input signal to create an internal input signal, the signal controlled oscillator generating the output clock in response to the internal input signal.

18. A The signal controlled oscillator system comprising:

a signal controlled oscillator configured to generate an output clock having an actual period in response to an input signal;

a phase controller coupled to receive the output clock, the phase controller being configured to generate a control signal representative of cycle-to-cycle deviations in the actual period of the output clock, wherein the phase controller includes an amplifier configured to generate a pair of complementary clock signals in response to the output clock; and

a feedback line for transmitting the control signal to the signal controlled oscillator.

19. The signal controlled oscillator system of claim 18, wherein the amplifier is configured to provide the complementary clock signals with a full signal swing between ground and a regulated supply voltage.

20. The signal controlled oscillator system of claim 18, wherein the phase controller further includes a period measurement circuit configured to generate a pair of period measurement signals in response to the complementary clock signals, wherein each of the period measurement signals has a peak magnitude representative of the actual period.

21. The signal controlled oscillator system of claim 20, wherein the phase controller further includes a dual peak detector configured to generate the control signal in response to the period measurement signals.

22. The signal controlled oscillator system of claim 20, wherein the period measurement circuit includes a pair of capacitors that are alternately charged and discharged in response to the complementary clock signals to create the period measurement signals.

23. The signal controlled oscillator system of claim 20, wherein the period measurement circuit includes:

a first capacitor;

a second capacitor;

a resistor;

a first transistor coupling the first capacitor to the resistor, wherein the first transistor is controlled by a first one of the complementary clock signals; and

a second transistor coupling the second capacitor to the resistor, wherein the second transistor is controlled by a second one of the complementary clock signals.

24. A signal controlled oscillator system of comprising:

a signal controlled oscillator configured to generate an output clock having an actual period in response to an input signal;

a phase controller coupled to receive the output clock, the phase controller being configured to generate a control signal representative of cycle-to-cycle deviations in the actual period of the output clock;

a feedback line for transmitting the control signal to the signal controlled oscillator;

a phase comparator coupled to receive the output clock and a reference clock signal, the phase comparator being configured to generate an error signal representative of the difference between the output clock and the reference clock signal; and

a loop filter coupled the phase comparator, the loop filter being configured to generate the input signal in response to the error signal.

25. A method of operating a signal controlled oscillator that generates an output clock, the method comprising:

measuring a first period of the output clock;

measuring a second period of the output clock, wherein the first period is a previous period with respect to the second period;

generating a feedback signal representative of a deviation between the first and second periods; and

adjusting a third period of the output clock in response to the feedback signal.

26. The method of claim 25, wherein the adjusting reduces a deviation between the second period and the third period of the output clock.