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Synchronous data serialization circuit

  • US 6,614,371 B2
  • Filed: 07/19/2001
  • Issued: 09/02/2003
  • Est. Priority Date: 07/19/2001
  • Status: Active Grant
First Claim
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1. A data processing circuit comprising:

  • a first clocked data storage circuit receiving a first data bit and a clock signal, the first clocked data storage circuit having a first stored output for transmitting a first stored data bit;

    a delay circuit receiving a second data bit, the delay circuit transmitting a delayed data signal, wherein delay circuit delays the second data bit by approximately one-half of the period of the clock signal;

    a second clocked data storage circuit receiving the delayed data signal and the clock signal, the second clocked data storage circuit having a second storage output for transmitting a second stored data bit; and

    a multiplexer having a first input coupled to the first stored output, a second input coupled to the second stored output, and a select input coupled to the clock signal.

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