Synchronous data serialization circuit
First Claim
1. A data processing circuit comprising:
- a first clocked data storage circuit receiving a first data bit and a clock signal, the first clocked data storage circuit having a first stored output for transmitting a first stored data bit;
a delay circuit receiving a second data bit, the delay circuit transmitting a delayed data signal, wherein delay circuit delays the second data bit by approximately one-half of the period of the clock signal;
a second clocked data storage circuit receiving the delayed data signal and the clock signal, the second clocked data storage circuit having a second storage output for transmitting a second stored data bit; and
a multiplexer having a first input coupled to the first stored output, a second input coupled to the second stored output, and a select input coupled to the clock signal.
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Abstract
In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.
40 Citations
30 Claims
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1. A data processing circuit comprising:
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a first clocked data storage circuit receiving a first data bit and a clock signal, the first clocked data storage circuit having a first stored output for transmitting a first stored data bit;
a delay circuit receiving a second data bit, the delay circuit transmitting a delayed data signal, wherein delay circuit delays the second data bit by approximately one-half of the period of the clock signal;
a second clocked data storage circuit receiving the delayed data signal and the clock signal, the second clocked data storage circuit having a second storage output for transmitting a second stored data bit; and
a multiplexer having a first input coupled to the first stored output, a second input coupled to the second stored output, and a select input coupled to the clock signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A data processing circuit comprising:
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a first data path for processing first data, the first data path including a first data storage circuit;
a second data path for processing second data, the second data path including a second data storage circuit;
a multiplexer having a first input coupled to the first data path and a second input coupled to the second data path, the multiplexer having a select input coupled to a clock signal; and
a delay circuit configured to delay storage of the second data in the second data storage circuit, wherein the delay is approximately one-half the period of the clock signal, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A synchronous data serialization circuit comprising:
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a first clocked data storage circuit coupled to receive a first data bit and a clock signal, the first clocked data storage circuit storing the first data bit in response to receiving a first transition of the clock signal, the first clocked data storage circuit having a first storage circuit output for transmitting the stored first data bit;
a delay circuit coupled to receive a second data bit, the delay circuit generating a delayed data signal, wherein the delay is approximately one-half the period of the clock signal;
a second clocked data storage circuit coupled to receive the delayed data signal and the clock signal, the second clocked data storage circuit storing the delayed data signal in response to receiving a second transition of the clock signal, the second clocked data storage circuit having a second storage circuit output for transmitting the stored delayed data signal; and
a multiplexer having a first input coupled to the first storage circuit output to receive the stored first data bit, a second input coupled to the second storage circuit output to receive the stored delayed data signal, a select input coupled to the clock signal, and a serial data output. - View Dependent Claims (18, 19, 20, 21, 22, 30)
an optical input system;
a demultiplexer;
an CMOS processor;
a multiplexer including a synchronous data serialization circuit of claim 17; and
an optical output system.
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23. A method of serializing data comprising:
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storing a first data bit in a first clocked data storage circuit in response to a first clock edge;
delaying a second data bit by approximately one-half the period of the clock signal;
storing the delayed second data bit in a second clocked data storage circuit in response to a second clock edge; and
coupling the stored first data bit to a serial output during a first portion of a clock signal, and coupling the stored delayed second data bit to the serial output during a second portion of the clock signal. - View Dependent Claims (24, 25)
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26. A synchronous data serialization circuit comprising:
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means for storing a first data bit in response to a first clock edge of a clock;
means for delaying a second data bit;
means for storing the delayed second data bit in response to a second clock edge of the clock; and
multiplexer means for selectively transmitting the first and second stored data bits in response to the clock. - View Dependent Claims (27)
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28. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:
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first circuitry implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry being configured to receive an input signal having a first frequency and to generate an output signal having a second frequency lower than the first frequency;
second circuitry implemented using conventional complementary metal-oxide semiconductor (CMOS) logic, the second circuitry being configured to receive and process the output signal having the second frequency; and
third circuitry implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic, the third circuitry being configured to receive an input signal having a first frequency and to generate an output signal having a second frequency higher than the first frequency, the third circuitry further comprising;
a first data path for processing first data, the first data path including a first data storage circuit;
a second data path for processing second data, the second data path including a second data storage circuit;
a multiplexer having a first input coupled to the first data path and a second input coupled to the second data path, the multiplexer having a select input coupled to a clock signal; and
a delay circuit configured to delay storage of the second data in the second data storage circuit. - View Dependent Claims (29)
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Specification