Sigma-delta analog-to-digital converter having improved reference multiplexer

• US 6,614,375 B2
• Filed: 08/08/2002
• Issued: 09/02/2003
• Est. Priority Date: 09/19/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hochschild, James R.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US10/214,992
• Publication Number:
  US 20030052806A1
• Time in Patent Office: 390 Days
• Field of Search: 341/143, 341/118, 341/144, 341/155, 341/139, 341/154
• US Class Current: 341/143
• CPC Class Codes: H03M 3/34 by chopping
• CPC Class Codes: H03M 3/356 Offset or drift compensation removal of offset already present on the analogue input signal H03M3/494
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path

Abstract

A low power, sigma-delta analog-to-digital converter having an improved reference multiplexer that eliminates noise in a reference voltage signal. The sigma-delta analog-to-digital converter includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of its differential input to its differential output, (2) cross-coupling of its differential input to its differential output, and (3) setting of the differential output to a fixed voltage to discharge the parasitic capacitance associated its differential output every clock cycle. This last mode of operation eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation; while a clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation.

Claims

1. A low-noise, sigma-delta analog-to-digital converter having a differential reference voltage input, a first differential input, and a first and second clock signal input, comprising:

a passive filter circuit having a first differential output, the passive filter circuit coupled to receive the differential reference voltage input;

a differential multiplexer coupled to receive the first clock signal, the differential multiplexer having a second differential input and second and third differential output, the second differential input coupled to receive the first differential output of the passive filter circuit, each second differential output having an inherent parasitic capacitance, the differential multiplexer including a mode of operation whereby the parasitic capacitance of the second differential output discharges every clock cycle;

a sigma-delta integrator coupled to receive the first differential input, the first and second clock signals, and the second differential output of the differential multiplexer; and

a comparator coupled to the output of the sigma-delta integrator to provide a decision signal, the differential multiplexer coupled to receive the decision signal.

2. The low noise, sigma-delta analog-to-digital converter as recited in claim 1 wherein the differential multiplexer, comprising:

a first sub-circuit portion coupled to receive the clock signal input and the decision signal to provide the third differential output and a first, second, third, and fourth control signal; and

a second sub-circuit portion coupled between the second differential input and the second differential output, the second sub-circuit portion coupled to receive the first, second, third and fourth control signals to provide a first, second and third mode of operation, the first mode of operation to directly couple the second differential input to the second differential output, the second mode of operation to cross-couple the second differential input to the second differential output, the third mode of operation to couple the second differential output to a predetermined voltage to discharge the inherent parasitic capacitance in the second differential output.

3. The differential multiplexer as recited in claim 2, wherein the first circuit portion comprising:

a first inverter coupled to the clock signal input;

a second inverter coupled to the decision signal;

a third inverter coupled to the second inverter;

a first pair of NAND gates including a first and second NAND gate, each NAND gate having a first and second input and an output, the output of the first inverter coupled to the first input of the first NAND gate and the first input of the second NAND gate, the output of the second inverter coupled to the second input of the first NAND gate, the output of the third inverter coupled to the second input of the second NAND gate;

a first latch, having a first and second node, coupled to receive the output of the first NAND gate to generate the first and the second control signal at the first and second node; and

a second latch, having a third and fourth node, coupled to receive the output of the second NAND gate to generate the third and fourth control signal at the third and fourth node.

4. The differential multiplexer as recited in claim 3, wherein the a first latch comprising:

a fourth inverter coupled to the output of the first NAND gate;

a second pair of cross-coupled NAND gates including a third and fourth NAND gate, each NAND gate having a first and second input and an output, the first input of the third NAND gate coupled to the output of the first NAND gate, the first input of the fourth NAND gate coupled to the output of the fourth inverter;

a fifth inverter coupled to the output of the third NAND gate;

a sixth inverter coupled to the output of the fifth inverter to form a first node, the output of the sixth inverter coupled to the second input of the fourth NAND gate;

a seventh inverter coupled to the output of the fourth NAND gate to form a second node;

an eighth inverter coupled to the output of the seventh inverter, the output of the eighth inverter coupled to the second input of the third NAND gate; and

a ninth inverter coupled to the output of the eighth inverter to provide a pulse output at the third differential output.

5. The differential multiplexer as recited in claim 3, wherein the second latch comprising:

a fourth inverter coupled to the output of the first NAND gate;

a second pair of cross-coupled NAND gates including a third and fourth NAND gate, each NAND gate having a first and second input and an output, the first input of the third NAND gate coupled to the output of the first NAND gate, the first input of the fourth NAND gate coupled to the output of the fourth inverter;

a fifth inverter coupled to the output of the third NAND gate;

a sixth inverter coupled to the output of the fifth inverter to form a first node, the output of the sixth inverter coupled to the second input of the fourth NAND gate;

a seventh inverter coupled to the output of the fourth NAND gate to form a second node;

an eighth inverter coupled to the output of the seventh inverter, the output of the eighth inverter coupled to the second input of the third NAND gate; and

a ninth inverter coupled to the output of the eighth inverter to provide a pulse output at the third differential output.

6. The differential multiplexer as recited in claim 2, wherein the a second circuit portion comprising:

a first transistor pair, including a first NMOS transistor and a first PMOS transistor, coupled directly between the second differential input and the second differential output, each transistor having a gate, a drain, and a source;

a second transistor pair, including a second NMOS transistor and a second PMOS transistor, cross-coupled between the second differential input and the second differential output, each transistor having a gate, a drain, and a source; and

the first sub-circuit portion for controlling the second sub-circuit portion wherein the first, second, third, and fourth nodes couple to the gates of the first NMOS transistor, the second PMOS transistor, the second NMOS transistor, the first PMOS transistor, respectively.

7. A differential multiplexer having a differential input, a differential output, a clock signal input, and a decision signal input, comprising:

a first sub-circuit portion including

a first inverter coupled to the clock signal input,

a second inverter coupled to the decision signal input,

a third inverter coupled to the second inverter,

a first pair of NAND gates including a first and second NAND gate, each NAND gate having a first and second input and an output, the output of the first inverter coupled to the first input of the first NAND gate and the first input of the second NAND gate, the output of the second inverter coupled to the second input of the first NAND gate, the output of the third inverter coupled to the second input of the second NAND gate,

a fourth inverter coupled to the output of the first NAND gate,

a second pair of cross-coupled NAND gates including a third and fourth NAND gate, each NAND gate having a first and second input and an output, the first input of the third NAND gate coupled to the output of the first NAND gate, the first input of the fourth NAND gate coupled to the output of the fourth inverter,

a fifth inverter coupled to the output of the third NAND gate,

a sixth inverter coupled to the output of the fifth inverter to form a first node, the output of the sixth inverter coupled to the second input of the fourth NAND gate,

a seventh inverter coupled to the output of the fourth NAND gate to form a second node,

an eighth inverter coupled to the output of the seventh inverter, the output of the eighth inverter coupled to the second input of the third NAND gate,

a ninth inverter coupled to the output of the second NAND gate,

a third pair of cross-coupled NAND gates including a fifth and sixth NAND gate, each NAND gate having a first and second input and an output, the first input of the fifth NAND gate coupled to the output of the second NAND gate, the first input of the sixth NAND gate coupled to the output of the ninth inverter,

a tenth inverter coupled to the output of the fifth NAND gate,

a eleventh inverter coupled to the output of the tenth inverter to form a third node, the output of the eleventh inverter coupled to the second input of the sixth NAND gate,

a twelfth inverter coupled to the output of the sixth NAND gate to form a fourth node,

a thirteenth inverter coupled to the output of the twelfth inverter, the output of the thirteenth inverter coupled to the second input of the fifth NAND gate; and

a second circuit portion including

a first transistor pair, including a first NMOS transistor and a first PMOS transistor, coupled directly between the differential input and the differential output, each transistor having a gate, a drain, and a source,

a second transistor pair, including a second NMOS transistor and a second PMOS transistor, cross-coupled between the differential input and the differential output, each transistor having a gate, a drain, and a source,

the first sub-circuit portion for controlling the second sub-circuit portion wherein the first, second, third, and fourth nodes couple to the gates of the first NMOS transistor, the second PMOS transistor, the second NMOS transistor, the first PMOS transistor, respectively.