Liquid crystal display having a dummy source pad and method for manufacturing the same

• US 6,614,500 B2
• Filed: 03/11/2002
• Issued: 09/02/2003
• Est. Priority Date: 03/03/1997
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Jeom Jae
• Primary Examiner(s): CHOWDHURY, TARIFUR RASHID
• Application Number:
  US10/093,454
• Publication Number:
  US 20020101548A1
• Time in Patent Office: 540 Days
• Field of Search: 345/43, 345/46, 345/54, 345/147, 345/42, 345/143, 345/152, 345/139, 345/149, 257/59, 257/72
• US Class Current: 349/152
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

An active panel of a liquid crystal display having a thin film transistor and a pixel electrode arranged in a matrix pattern has a double gate us line. On a substrate, a gate bus line, a gate electrode and a gate pad are formed using a first metal such as aluminum having low electrical resistance and a second metal such as chromium having surface stability. Then, a dummy source bus line and a dummy source pad are formed prior to forming a source bus line and a source pad so as to eliminate line disconnection due to the cracks thereof and to thereby reduce the defects of the active panel and the increase production yield of the manufacturing process.

Claims

1. A method of manufacturing a liquid crystal display, the method comprising:

providing a substrate including a source pad region;

forming a gate bus line on the substrate;

forming an insulating layer on the gate bus line;

forming a dummy source pad located substantially at an area of the source pad region on the insulating layer; and

forming a source bus line and a source pad arranged to cover the dummy source pad.

2. The method according to claim 1, wherein forming a dummy source pad includes forming at least one of an intrinsic semiconductor layer or a doped semiconductor layer.

3. The method according to claim 1, wherein forming a dummy source pad includes forming a dummy source bus line.

4. The method according to claim 3, wherein the dummy source pad is the same material as that of the dummy source bus line.

5. The method according to claim 3, wherein the source bus line is formed directly on the dummy source bus line.

6. The method according to claim 1, wherein the source bus line and the source pad cover completely the dummy source pad.

7. The method according to claim 1, wherein the source pad is formed directly on the dummy source pad.

8. The method according to claim 1, further comprising:

forming a low resistance gate electrode on the substrate; and

forming a second gate electrode over the low resistance gate electrode.

9. The method according to claim 1, further comprising forming a low resistance gate bus line under the gate bus line.

10. The method according to claim 1, further comprising:

forming a low resistance gate pad on the substrate; and

forming a second gate pad over the low resistance gate pad.

11. A liquid crystal display comprising:

a substrate including a source pad region;

a gate bus line on the substrate and including a first conductive material;

an insulating layer on the gate bus line;

a dummy source pad disposed on the insulating layer at a location of the source pad region;

a source pad including a second conductive material which is different from the first conductive material and is disposed on the dummy source pad; and

a source bus line connected to the source pad.

12. The liquid crystal display according to claim 11, further comprising a dummy source bus line located under the source bus line and connected with the source pad.

13. The liquid crystal display according to claim 12, wherein the source bus line is formed directly on the dummy source bus line.

14. The liquid crystal display according to claim 11, wherein the source pad completely covers the dummy source pad.

15. The liquid crystal display according to claim 11, wherein the source pad is formed directly on the dummy source pad.

16. The liquid crystal display according to claim 11, further comprising:

a low resistance gate electrode on the substrate; and

a second gate electrode on the low resistance gate electrode.

17. The liquid crystal display according to claim 11, further comprising a low resistance gate bus line underneath the gate bus line.

18. The liquid crystal display according to claim 11, further comprising:

a low resistance gate pad on the substrate; and

a second gate pad on the low resistance gate pad.

19. The liquid crystal display according to claim 11, wherein the first conductive material includes at least one of chromium, molybdenum, tantalum or antimony.

20. The liquid crystal display according to claim 11, wherein the second conductive material includes chromium or chromium alloy.

21. The liquid crystal display according to claim 11, wherein the dummy source pad includes at least one of an intrinsic semiconductor layer or a doped semiconductor layer.