Semiconductor memory and method for driving the same

• US 6,614,678 B2
• Filed: 07/17/2001
• Issued: 09/02/2003
• Est. Priority Date: 07/25/2000
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kato, Yoshihisa, Shimada, Yasuhiro
• Primary Examiner(s): Nguyen, Van Thu
• Application Number:
  US09/905,893
• Publication Number:
  US 20020018358A1
• Time in Patent Office: 777 Days
• Field of Search: 365/145, 365/149
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film

Abstract

A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the successively connected plural ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors. A set line is connected to the other end of the successively connected plural ferroelectric capacitors. A bit line is connected to the drain of the reading transistor at one end thereof. A reset line is connected to the source of the reading transistor at one end thereof. A plurality of word lines respectively corresponding to the plural ferroelectric capacitors are provided perpendicularly to the bit line, so as to select a ferroelectric capacitor from the plural ferroelectric capacitors for data write or data read.

Claims

1. A semiconductor memory comprising:

a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of said plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of said ferroelectric film of a selected ferroelectric capacitor selected from said plurality of ferroelectric capacitors;

a set line connected to the other end of said plurality of successively connected ferroelectric capacitors;

a bit line connected to a drain of said reading transistor at one end thereof and to a control line at another end thereof;

a reset line connected to a source of said reading transistor at one end thereof; and

a plurality of word lines respectively corresponding to said plurality of ferroelectric capacitors for selecting said selected ferroelectric capacitor from said plurality of ferroelectric capacitors for data write or data read.

2. A semiconductor memory comprising:

a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of said plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of said ferroelectric film of a selected ferroelectric capacitor selected from said plurality of ferroelectric capacitors;

a set line connected to the other end of said plurality of successively connected ferroelectric capacitors;

a bit line connected to a drain of said reading transistor at one end thereof;

a reset line connected to a source of said reading transistor at one end thereof; and

a plurality of word lines respectively corresponding to said plurality of ferroelectric capacitors for selecting said selected ferroelectric capacitor from said plurality of ferroelectric capacitors for data write or data read,

wherein a first division voltage obtained by dividing a reading voltage applied to said set line on the basis of a ratio between capacitance of said selected ferroelectric capacitor and gate capacitance of said reading transistor is induced to the gate of said reading transistor, and

said reading voltage is set to such magnitude that a relationship of VR>

VT>

VS holds among a threshold voltage VT of said reading transistor, a first division voltage vs induced to the gate of said reading transistor when a data is written in said selected ferroelectric capacitor and a first division voltage VR induced to the gate of said reading transistor when a data is not written in said selected ferroelectric capacitor.

3. A semiconductor memory comprising:

a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of said plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of said ferroelectric film of a selected ferroelectric capacitor selected from said plurality of ferroelectric capacitors;

a set line connected to the other end of said plurality of successively connected ferroelectric capacitors;

a bit line connected to a drain of said reading transistor at one end thereof;

a reset line connected to a source of said reading transistor at one end thereof; and

a plurality of word lines respectively corresponding to said plurality of ferroelectric capacitors for selecting said selected ferroelectric capacitor from said plurality of ferroelectric capacitors for data write or data read,

wherein a second division voltage obtained by dividing a reading voltage applied to said set line on the basis of a ratio between capacitance of said selected ferroelectric capacitor and gate capacitance of said reading transistor is induced between an upper electrode and a lower electrode of said selected ferroelectric capacitor, and

said reading voltage is set to such magnitude that said second division voltage does not exceed a coercive voltage of said selected ferroelectric capacitor.

4. The semiconductor memory of claim 3, further comprising a plurality of selecting transistors respectively connected to said plurality of ferroelectric capacitors in parallel whose gates are respectively connected to said plurality of word lines.

5. A semiconductor memory comprising:

a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of said plurality of successively connected ferroelectric capacitors for reading a data by detecting the displacement of the polarization of said ferroelectric film of a selected ferroelectric capacitor selected from said plurality of ferroelectric capacitors;

a set line connected to the other end of said plurality of successively connected ferroelectric capacitors;

a bit line connected to a drain of said reading transistor at one end thereof;

a reset line connected to a source of said reading transistor at one end thereof;

a plurality of word lines respectively corresponding to said plurality of ferroelectric capacitors for selecting said selected ferroelectric capacitor from said plurality of ferroelectric capacitors for data write or data read; and

a load resistance connected to the other end of said bit line at one end thereof, and a power voltage is applied to the other end thereof,

wherein said semiconductor memory further comprises comparison means for comparing, with a reference voltage, voltage change caused at both ends of said load resistance owing to a current flowing between the drain and the source of said reading transistor in accordance with the displacement of the polarization of said ferroelectric film of said selected ferroelectric capacitor.

6. The semiconductor memory of claim 5, further comprising a load resistance connected, at one end thereof, to the other end of said bit line.

7. The semiconductor memory of claim 6,

wherein said load resistance is a MOS transistor.

8. A semiconductor memory comprising:

a first memory cell block including a first capacitors group composed of a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a first reading transistor whose gate is connected to one end of said plurality of ferroelectric capacitors composing said first capacitors group for reading a data by detecting the displacement of the polarization of said ferroelectric film of a selected ferroelectric capacitor selected from said plurality of ferroelectric capacitors;

a second memory cell block including a second capacitors group composed of a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a second reading transistor whose gate is connected to one end of said plurality of ferroelectric capacitors composing said second capacitors group for reading a data by detecting the displacement of the polarization of said ferroelectric film of a selected ferroelectric capacitor selected from said plurality of ferroelectric capacitors, said second memory cell block provided along a word line direction of said first memory cell block;

a set line connected to the other end of said plurality of ferroelectric capacitors composing said first capacitors group and to the other end of said plurality of ferroelectric capacitors composing said second capacitors group;

a first bit line connected to a drain of said first reading transistor at one end thereof;

a second bit line connected to a drain of said second reading transistor at one end thereof;

a first load resistance connected to the other end of said first bit line at one end thereof and connected to a power voltage at the other end thereof;

a second load resistance connected to the other end of said second bit line at one end thereof and connected to the power voltage at the other end thereof;

a reset line connected to a source of said first reading transistor and a source of said second reading transistor at one end thereof; and

a plurality of word lines respectively corresponding to said ferroelectric capacitors, which are arranges in said word line and are part of said plurality of ferroelectric capacitors composing said first capacitors group and said second capacitors group, for selecting said selected ferroelectric capacitors from said plurality of ferroelectric capacitors for data write of data read,

wherein said semiconductor memory further comprises comparison means for comparing, in applying a reading voltage to said set line, first voltage change caused at both ends of said first load resistance owing to a current flowing between the drain and the source of said first reading transistor with second voltage change caused at both ends of said second load resistance owing to a current flowing between the drain and the source of said second reading transistor.