Semiconductor integrated circuit and nonvolatile memory element

• US 6,614,684 B1
• Filed: 01/28/2000
• Issued: 09/02/2003
• Est. Priority Date: 02/01/1999
• Status: Expired due to Term

• Current Assignee: Tessera Advanced Technologies Inc (Adeia Inc.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Okuyama, Kousuke, Shukuri, Shoji, Komori, Kazuhiro, Kubota, Katsuhiko
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/493,280
• Time in Patent Office: 1,313 Days
• Field of Search: 365/185.03, 365/185.04, 365/185.05, 365/185.08, 365/185.33, 257/314, 257/318
• US Class Current: 365/185.05
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2216/08 Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data. A word line voltage in a readout mode is set to be substantially equal to a threshold voltage in a thermal equilibrium state (an initial threshold voltage), and also to be substantially equal to the average value of a low threshold voltage value and a high threshold voltage value. Thus, a data retention capability is enhanced to realize lowering in the rate of readout faults.

Claims

1. A semiconductor integrated circuit device on a semiconductor substrate, comprising:

a nonvolatile memory which comprises a nonvolatile memory cell including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element having a source, a drain, a floating gate and a control gate, the control gates of the pair of nonvolatile memory elements being coupled to a word line, the drains of the pair of nonvolatile memory elements being respectively coupled to a pair of complementary data lines, and in which information items read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements are amplified by a sense amplifier,

wherein a selection voltage which is applied to the word line for the purpose of information readout from the nonvolatile memory elements is substantially equalized to an initial threshold voltage of the nonvolatile memory elements,

wherein the source and the drain of each nonvolatile memory element are formed of a first and a second semiconductor region of a second conductivity type which are provided in a third semiconductor region of a first conductivity type in the semiconductor substrate;

wherein the floating gate of each nonvolatile memory element is formed of a conductive layer which is arranged over a channel defined between the source and the drain, through a first gate insulating film; and

wherein the control gate of each nonvolatile memory element is formed of a fourth semiconductor region of the second conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film.

8. A semiconductor integrated circuit device according to claim 1, wherein:

the mutually different logical states of the pair of nonvolatile memory elements are determined by a relatively low threshold voltage state of one of the nonvolatile memory elements and a relatively high threshold voltage state of the other one of the nonvolatile memory elements; and

the initial threshold voltage is a voltage which is approximately an average value between the relatively low threshold voltage and the relatively high threshold voltage.

9. A semiconductor integrated circuit device according to claim 1, wherein the floating gate of each nonvolatile memory element is formed with an impurity of the first conductivity type.

10. A semiconductor integrated circuit device according to claim 9, further comprising:

a volatile storage circuit in which the control information read out from the nonvolatile memory is stored; and

a volatile memory which includes first volatile memory cells and second volatile memory cells and in which one of the first volatile memory cells is replaced with one of the second volatile memory cells in accordance with the control information transferred to and stored in the volatile storage circuit.

11. A semiconductor integrated circuit device according to claim 10, wherein the volatile memory is a cache memory connected to a central processing unit.

12. A semiconductor integrated circuit device according to claim 9, wherein the nonvolatile memory constructs a part or a whole of a programmable logic circuit whose stored information determines an output logical function corresponding to an input.

2. A semiconductor integrated circuit device on a semiconductor substrate, comprising:

a nonvolatile memory which comprises a nonvolatile memory cell including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element having a MIS transistor including a drain, a source and a floating gate, and a control gate, the control gates of the pair of nonvolatile memory elements being connected in common to a word line, the drains of the pair of MIS transistors being respectively coupled to a pair of complementary data lines, and in which control information read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements are differentially amplified by a sense amplifier,

wherein a difference voltage between a selection voltage which is applied to the word line for the purpose of the information readout from the nonvolatile memory elements and an initial threshold voltage of the nonvolatile memory elements is a voltage smaller than a voltage width of an input voltage range within which the sense amplifier is subjected to a transient response operation,

wherein the source and the drain of each MIS transistor are formed of a first and a second semiconductor region of a second conductivity type which are provided in a third semiconductor region of a first conductivity type in the semiconductor substrate;

wherein the floating gate of each MIS transistor is formed of a conductive layer which is arranged over a channel defined between the source and the drain, through a first gate insulating film; and

wherein the control gate of each nonvolatile memory element is formed of a fourth semiconductor region of the second conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film.

3. A semiconductor integrated circuit device according to claim 2, wherein:

the mutually different logical states of the pair of nonvolatile memory elements are determined by a relatively low threshold voltage state of one of the nonvolatile memory elements and a relatively high threshold voltage state of the other one of the nonvolatile memory elements; and

the initial threshold voltage is a voltage which is approximately an average value between the relatively low threshold voltage and the relatively high threshold voltage.

4. A semiconductor integrated circuit device according to claim 2, wherein the floating gate of the MIS transistor is formed with an impurity of the first conductivity type.

5. A semiconductor integrated circuit device according to claim 4, further comprising:

a volatile storage circuit in which the control information read out from the nonvolatile memory on the pair of complementary data lines is stored; and

a volatile memory which comprises first volatile memory cells and second volatile memory cells and in which one of the first volatile memory cells is replaced with one of the second volatile memory cells in accordance with the control information transferred to and stored in the volatile storage circuit.

6. A semiconductor integrated circuit device according to claim 5, wherein the volatile memory is a cache memory connected to a central processing unit.

7. A semiconductor integrated circuit device according to claim 4, wherein the nonvolatile memory constructs a part or a whole of a programmable logic circuit whose stored information determines an output logical function corresponding to an input.

13. A semiconductor integrated circuit device comprising:

a memory array which includes a plurality of first volatile memory cells and a second volatile memory cell;

an electrically erasable and programmable nonvolatile memory in which control information for the memory array is stored, wherein the electrically erasable and programmable nonvolatile memory includes a plurality of single layer gate memory elements, each of which comprises;

a MIS transistor with a gate electrode as a floating gate,

a semiconductor region in a semiconductor substrate as a control gate, and

an insulating film disposed between a conductive layer extending from the floating gate and the semiconductor region;

a volatile storage circuit in which control information stored in the nonvolatile memory is to be stored; and

a signal line which transmits a control signal for giving commands in parallel for an operation of reading the control information from the nonvolatile memory and an operation of writing the control information into the volatile storage circuit;

wherein one of the plurality of first volatile memory cells is replaced with the second volatile memory cell in accordance with the control information transferred to and stored in the volatile storage circuit.

14. A semiconductor integrated circuit device according to claim 13, wherein the control signal is a reset signal.

15. A semiconductor integrated circuit device according to claim 14, wherein the memory array includes memory cells of a dynamic random access memory.

16. A semiconductor integrated circuit device according to claim 14, wherein the memory array includes memory cells of a static random access memory.

17. A semiconductor integrated circuit device according to claim 16, wherein the memory array is a cache memory.

18. A semiconductor integrated circuit device according to claim 14, wherein the nonvolatile memory is configured of memory cells which are coupled in a differential form.

19. A CMOS semiconductor integrated circuit device comprising:

a memory array including first and second volatile memory cells;

an electrically programmable and erasable nonvolatile memory which includes a plurality of memory elements to be stored therein information for the memory array, the information including a plurality of bits, each being stored in a pair of memory elements in the plurality of memory elements, and each memory element being a single layer gate;

a register to be latched therein the information in the electrically programmable and erasable non-volatile memory; and

a control circuit which controls reading operation of the electrically programmable and erasable non-volatile memory and writing operation of the register,

wherein one of the first volatile memory cells is replaced with one of the second volatile memory cells in accordance with the information transferred to the register.

20. A CMOS semiconductor integrated circuit device according to claim 19, wherein each memory element has a floating electrode as the single layer gate and a control electrode formed of a semiconductor region in a semiconductor substrate where the CMOS semiconductor integrated circuit device is formed.

21. A CMOS semiconductor integrated circuit device according to claim 20, wherein the control circuit is controlled by a reset signal.

22. A semiconductor integrated circuit device on a semiconductor substrate, comprising:

an internal CMOS logic circuit which includes MIS transistors having gate electrodes of a first level polycrystalline silicon layer; and

an electrically programmable and erasable nonvolatile memory which includes memory cells each having a pair of memory elements, each memory element including a floating gate of the first level polycrystalline silicon layer and a control gate of a semiconductor region in the semiconductor substrate.

23. A semiconductor integrated circuit device according to claim 22, wherein the MIS transistors of the internal CMOS logic circuit have gate insulating films which are thicker than that of the memory cells.

24. A semiconductor integrated circuit device according to claim 23, further comprising:

an external input/output circuit coupled to the internal CMOS logic circuit,

wherein the external input/output circuit has MIS transistors having gate insulating films which are the same thickness of gate insulating films of the memory cells.

25. A semiconductor integrated circuit device on a semiconductor substrate, comprising:

a plurality of nonvolatile memory cells each including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element having;

a source of a first semiconductor region of a first conductivity type in a second semiconductor region of a second conductivity type in the semiconductor substrate,

a drain of a third semiconductor region of the first conductivity type in the second semiconductor region of the second conductivity type in the semiconductor substrate,

a first gate insulating film disposed over a channel region defined between the first semiconductor region and the third semiconductor region,

a floating gate of a conductive layer over the first gate insulating film, and

a control gate of a fourth semiconductor region of the first conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film,

a word line coupled to the pair of control gates of the pair of electrically programmable nonvolatile memory elements;

a selection voltage which is applied to the word line for the purpose of information readout from the pair of electrically programmable nonvolatile memory elements being substantially equalized to an initial threshold voltage of the pair of electrically programmable nonvolatile memory elements;

a pair of complementary data lines coupled to the drains of the pair of electrically programmable nonvolatile memory elements; and

a sense amplifier for amplifying information items read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements.

26. A semiconductor integrated circuit device on a semiconductor substrate, comprising:

a nonvolatile memory which comprises a nonvolatile memory cell including a pair of electrically programmable nonvolatile memory elements, each nonvolatile memory element including;

a MIS transistor having;

a source of a first semiconductor region of a first conductivity type in a second semiconductor region of a second conductivity type in the semiconductor substrate,

a drain of a third semiconductor region of the first conductivity type in the second semiconductor region of the second conductivity type in the semiconductor substrate,

a first gate insulating film disposed over a channel region defined between the first semiconductor region and the third semiconductor region, and

a floating gate of a conductive layer over the first gate insulating film, and

a control gate of a fourth semiconductor region of the first conductivity type in the semiconductor substrate which is arranged under a portion of the conductive layer extended from the floating gate, through a second gate insulating film;

a word line coupled to the control gate;

complementary data lines coupled to the drains of the pair of nonvolatile memory elements, respectively; and

a sense amplifier coupled to complementary data lines for differentially amplifying information read out on the pair of complementary data lines in accordance with mutually different logical states of the pair of nonvolatile memory elements,

wherein a difference voltage between a selection voltage which is applied to said word line for the purpose of the information readout from the nonvolatile memory elements and an initial threshold voltage of the pair of electrically programmable nonvolatile memory elements is a voltage smaller than a voltage width of an input voltage range within which the sense amplifier is subjected to a transient response operation.