Multiplexed chirp waveform synthesizer
First Claim
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1. A multiplexed waveform synthesizer for generating a desired chirp signal comprising:
- M parallel channels, where M=2k where k is a positive integer greater than 1, each channel comprising a chirp waveform synthesizer generating at an output a portion of a digital representation of the desired chirp signal; and
multiplexer means for multiplexing the M outputs to create a digital representation of the desired chirp signal.
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Abstract
A synthesizer for generating a desired chirp signal has M parallel channels, where M is an integer greater than 1, each channel including a chirp waveform synthesizer generating at an output a portion of a digital representation of the desired chirp signal; and a multiplexer for multiplexing the M outputs to create a digital representation of the desired chirp signal. Preferably, each channel receives input information that is a function of information representing the desired chirp signal.
36 Citations
18 Claims
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1. A multiplexed waveform synthesizer for generating a desired chirp signal comprising:
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M parallel channels, where M=2k where k is a positive integer greater than 1, each channel comprising a chirp waveform synthesizer generating at an output a portion of a digital representation of the desired chirp signal; and
multiplexer means for multiplexing the M outputs to create a digital representation of the desired chirp signal. - View Dependent Claims (6, 7, 8, 9, 15, 18)
where m is an integer between 0 and M−
1 identifying each channel, Pm(0) is the starting phase for each channel, Fm(0) is the starting frequency for each channel, and Km is the starting chirp rate for each channel.
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9. The multiplexed waveform synthesizer of claim 8 further comprising digital to analog converter for receiving said digital representation from said multiplexer to generate said chirp waveform.
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15. The multiplexed waveform synthesizer of claim 1 further comprising means for providing information representative of the desired chirp signal to each of said chirp waveform synthesizers.
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18. The multiplexed waveform synthesizer of claim 1 wherein the digital representation of the desired chirp signal is clocked at M dimes the clock rate of each channel'"'"'s waveform synthesizer.
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2. A multiplexed waveform synthesizer for generating a desired chirp signal comprising:
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M parallel channels, where M is an integer greater than 1, wherein each channel is a double accumulator chirp synthesizer for generating a portion of a digital representation of the desired chirp signal and comprises;
a frequency accumulator for generating an output representative of a desired frequency range;
a phase accumulator in series with said frequency accumulator for generating an instantaneous phase output representative of a desired waveform; and
a mapping device for transforming the output of said phase accumulator to a digital function of a sine wave at the frequency of said frequency accumulator, each said mapping device having an output;
multiplexer means for multiplexing the M outputs of said mapping devices to create a digital representation of the desired chirp signal; and
an initializor for receiving inputs representative of the desired chirp signal, said initializor having output means for providing input information to each of said chirp waveform synthesizers. - View Dependent Claims (3, 4, 5, 10, 11, 12, 13, 14, 16, 17)
where Fs(0), Ps(0), and Ks are the starting frequency, phase, and chirp rate for a single channel synthesizer to provide the desired output.
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12. The multiplexed waveform synthesizer of claim 4 where M=2k where k is a positive integer.
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13. The multiplexed waveform synthesizer of claim 5 where M=2k where k is a positive integer.
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14. The multiplexed waveform synthesizer of claim 11 where M=2k where k is a positive integer.
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16. The multiplexed waveform synthesizer of claim 11 further comprising a digital to analog converter connected in series with said multiplexer for creating an anolog chirp signal.
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17. The multiplexed waveform synthesizer of claim 16 wherein each accumulator is clocked at 1/M the clock rate at which the digital to analog converter is clocked.
Specification