FIR filter architecture for 100Base-TX receiver

• US 6,614,842 B1
• Filed: 07/13/2000
• Issued: 09/02/2003
• Est. Priority Date: 07/13/2000
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Chou, Gerchih, Tai, Gwo-Chung
• Primary Examiner(s): Tran, Khai
• Application Number:
  US09/615,116
• Time in Patent Office: 1,146 Days
• Field of Search: 375/232, 375/233, 375/236, 375/316, 375/350, 375/345, 708/322, 708/323, 708/229
• US Class Current: 375/232
• CPC Class Codes: H03H 17/06 Non-recursive filters

Abstract

A 100Base-TX receiver employs a finite impulse response (FIR) filter to provide both equalization and insertion loss compensation for an MLT-3 input signal. The FIR filter includes three delay stages, each delaying the input signal with an 8 ns delay (the period of one data cycle of the MLT-3 input signal), a set of three amplifiers for amplifying the delay stage outputs with gains C1, C2 and C3, and a summer for summing the outputs of the three amplifiers to produce a compensated, equalized MLT-3 signal. A low-pass filter filters the FIR filter output signal, and a data slicer digitizes the low-pass filter output during each data cycle to produce data representing the incoming MLT-3 as having one of six levels. An adaptive control signal processes the slicer output data to determine how to set the gains C1, C2 and C3 of the three FIR amplifiers to provide the correct amount of equalization and compensation. The adaptive control circuit also processes the slice data to adaptively adjust the phase of a clock signal controlling timing of the data slicer, to adaptively adjust an amount of baseline wander compensation provided to the MLT-3 signal, and to determine the value of data conveyed by the MLT-3 input signal.

Claims

1. An apparatus for receiving and processing a first waveform (SIG3) representing successive bits of a data sequence during successive data cycles, wherein a state of each successive bit of the data sequence is indicated by whether the first waveform transitions between voltage levels during a corresponding one of the data cycles, and wherein the apparatus produces an output digital data signal representing the data sequence, the apparatus comprising:

filter means for filtering the first waveform to provide equalization and gain control, thereby producing a second waveform (SIG5) representing successive bits of the data sequence during successive data cycles, wherein the state of each successive bit of the data sequence is indicated by whether the second waveform transitions between defined voltage levels during a corresponding one of the data cycles, wherein the filter means implements a filter function having N adjustable coefficients adjusted by coefficient control signals (C1, C2, C3) supplied as input to the filter means, wherein N is an integer greater than 2, wherein each of the N adjustable coefficients influences a relationship between the first and second waveforms;

a data slicer for repeatedly digitizing the second waveform in response to edges of a clock signal to produce data output indicating a voltage range of the second waveform;

a clock signal generator for supplying the clock signal to the data slicer with a phase determined by a phase control signal; and

an adaptive control circuit for processing the data output of the data slicer to produce and supply the coefficient control signals to the filter means, to produce and supply the phase control signal to the clock signal generator, and to produce the digital data signal.

2. The apparatus in accordance with claim 1 wherein the filter means comprises an N-stage finite impulse response (FIR) filter implementing the filter function.

3. The apparatus in accordance with claim 2 wherein the N-stage FIR filter comprises:

N delay stages connected in series for successively delaying the first waveform to produce a set of N first delayed waveforms (SIG31, SIG32, SIG33);

N amplifiers, each for amplifying a first delayed waveform output of a corresponding one of the delay stages to with a gain controlled by a separate one of the coefficient control signals to produce a set of N second delayed waveforms (SIG41, SIG42, SIG43);

means for summing the set of N second delayed waveforms to produce a third waveform (SIG4).

4. The apparatus in accordance with claim 3 wherein the filter means further comprises a low-pass filter for low-pass filtering the third waveform to produce the second waveform.

5. The apparatus in accordance with claim 3 wherein N is three.

6. The apparatus in accordance with claim 3 wherein the coefficient control signals produced by the adaptive control circuit adjust the gain of each of the N amplifiers to adaptively equalize the second waveform.

7. The apparatus in accordance with claim 6 wherein the coefficient control signals produced by the adaptive control circuit also adjusts the gains of N amplifiers to provide automatic gain control of the second waveform.

8. The apparatus in accordance with claim 5

wherein N is three, and

wherein a gain of one of the N amplifiers is a fixed multiple of a gain of another of the amplifiers.

9. The apparatus in accordance with claim 8 wherein the fixed multiple is within in a range of 0.1 to 1.

10. The apparatus in accordance with claim 3 wherein the clock signal generator also produces an analog signal (CONT3) controlling the delay of each of the delay stages.

11. The apparatus in accordance with claim 3 wherein each of the delay stages comprises a sample and hold circuit clocked by the clock signal.

12. The apparatus in accordance with claim 1 wherein N is equal to 3,

wherein the second waveform has three defined voltage levels,

wherein the data produced by the data slicer represents the voltage of the second waveform as residing in one voltage range of a set of three pairs of voltage ranges,

wherein each the pair of voltage ranges bounds a separate one of the three defined voltage levels, and

wherein the adaptive control circuit processes the data output of the data slicer corresponding to two successive data cycles of the second waveform to produce and supply the coefficient control signals to the filter means, to produce and supply the phase control signal to the clock signal generator, and to produce the output digital data signal.

13. A receiver for receiving and processing an input waveform (INPUT) representing successive bits of a data sequence during successive data cycles, wherein a state of each successive bit of the data sequence is indicated by whether the input waveform transitions between three voltage levels during a corresponding one of the data cycles, and wherein the receiver produces a digital data signal (DATA) representing the data sequence, the receiver comprising:

an attenuator for receiving and attenuating the input waveform to produce a first waveform (SIG1);

means for level shifting the first waveform in response to a second waveform (SIG2) to produce a third waveform (S1S3);

a finite impulse response (FIR) filter for filtering the third waveform to provide equalization and gain control, thereby producing a fourth waveform (SIG. 4) representing successive bits of the data sequence during successive data cycles, wherein the state of each successive bit of the data sequence is indicated by whether the second waveform transitions between defined voltage levels during a corresponding one of the data cycles, wherein the FIR filter implements a filter function having three coefficients adjusted by coefficient control signals (C1, C2, C3) supplied as input to the FIR filter,

a low-pass filter for filtering the fourth waveform to produce a fifth waveform (SIG5);

a data slicer for repeatedly digitizing the fifth waveform in response to edges of a clock signal to produce data (SLICE_DATA) indicating a voltage range of the second waveform;

a clock generator for supplying the clock signal to the data slicer with a phase determined by a phase control signal; and

an adaptive control circuit for processing the data produced by the data slicer to produce and supply the coefficient control signals as input to the FIR filter, to produce and supply the phase control signal to the clock generator, and to produce the digital data signal.

14. The receiver in accordance with claim 13 wherein the FIR filter comprises:

three delay stages connected in series for successively delaying the third waveform to produce a set of three first delayed waveforms (SIG31, SIG32, SIG33);

three amplifiers, each for amplifying a first delayed waveform output of a corresponding one of the three delay stages with a gain controlled by a separate one of the coefficient control signals to produce a set of three second delayed waveforms (SIG41, SIG42, SIG43);

means for summing the set of three second delayed waveforms to produce the fourth waveform.

15. The receiver in accordance with claim 14 wherein the coefficient control signals produced by the adaptive control circuit adjust amplifier gains such that the FIR filter adaptively equalizes the fifth waveform.

16. The receiver in accordance with claim 15 wherein the coefficient control signals produced by the adaptive control circuit also adjust amplifier gains such that the FIR filter provides automatic gain control for the fifth waveform.

17. The receiver in accordance with claim 16 wherein a gain of one of the three amplifiers is a fixed multiple of a gain of another of the three amplifiers.

18. The receiver in accordance with claim 14 wherein the clock signal generator also produces an analog signal controlling the delay of each of the delay stages.

19. The receiver in accordance with claim 14 wherein each of the delay stages comprises a sample and hold circuit clocked by the clock signal.

20. The receiver in accordance with claim 14 wherein the fifth waveform has three defined voltage levels,

wherein the data produced by the data slicer indicates the voltage of the fifth waveform as residing in one voltage range of a set of three pairs of voltage ranges,

wherein each the pair of voltage ranges bounds a separate one of the three defined voltage levels, and

wherein the adaptive control circuit processes the data output of the data slicer corresponding to two successive data cycles of the fifth waveform to produce and supply the coefficient control signals to the filter means, to produce and supply the phase control signal to the clock signal generator, and to produce the digital data signal.