DMA controller with dynamically variable access priority
First Claim
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1. A DMA controller including:
- a memory;
a common bus connected to the memory;
a plurality of devices connected to the common bus and accessible to the memory through the common bus;
bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and
bus-use reconcilement means for reconciling pluralities of bus-access made by the devices based on a detection result obtained by the bus monitor means.
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Abstract
A bus monitor section 8 calculates bus-occupancy rate for each of the DMA control sections 1 to 3 connected to a bus 5 in accordance with bus-use permission signals ack1 to ack3, respectively. Furthermore, a bus-use reconcilement section 6 changes manners of bus-use reconcilement control when the sum of a plurality of bus-occupancy rate exceeds “50”, a predetermined threshold. Thereby, this method avoids occurrences such that a specific device occupies the bus 5 or vice versa, a specific device cannot get access to the bus 5.
27 Citations
25 Claims
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1. A DMA controller including:
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a memory;
a common bus connected to the memory;
a plurality of devices connected to the common bus and accessible to the memory through the common bus;
bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and
bus-use reconcilement means for reconciling pluralities of bus-access made by the devices based on a detection result obtained by the bus monitor means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A DMA controller including:
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a memory;
a common bus connected to the memory;
a plurality of devices connected to the common bus and accessible to the memory through the common bus;
device monitor means for detecting operation-state of each of the devices; and
bus-use reconcilement means for reconciling pluralities of bus-access made by the devices based on a detection result obtained by the device monitor means. - View Dependent Claims (12, 13, 14, 15)
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16. A DMA controller including:
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a memory;
a common bus connected to the memory;
a plurality of devices connected to the common bus and accessible to the memory through the common bus;
bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and
DMA-transfer-method changing means for changing DMA transfer methods between the memory and at least one of the device in accordance with a detection result obtained by the bus monitor means. - View Dependent Claims (17, 18)
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19. A DMA controller including:
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a memory;
a common bus connected to the memory;
a plurality of devices connected to the common bus and accessible to the memory through the common bus;
bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and
mode-switch means for switching to low-power-consumption mode in accordance with a detection result obtained by the bus monitor means. - View Dependent Claims (20, 21, 22, 23)
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24. A DMA controller including:
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a memory having a plurality of memory blocks;
a common bus connected to the memory;
a plurality of devices connected to the common bus and accessible to the memory through the common bus;
bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and
memory controller means for controlling operation mode of each of the memory blocks in accordance with a detection result obtained by the bus monitor means. - View Dependent Claims (25)
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Specification