Method and apparatus for regulating write burst lengths

• US 6,615,308 B1
• Filed: 12/09/1999
• Issued: 09/02/2003
• Est. Priority Date: 12/09/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fanning, Blaise B.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/458,546
• Time in Patent Office: 1,363 Days
• Field of Search: 710/31, 710/33, 710/34, 710/35, 710/46, 710/60, 710/112, 710/116, 710/123, 710/105, 711/147, 711/151, 711/152, 711/154
• US Class Current: 711/105
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

In one embodiment, monitoring data traffic through a memory controller; and dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic.

Claims

1. A method, comprising:

monitoring data traffic through a memory controller;

dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic, the burst length including a first burst length and a second burst length; and

selecting the first burst length if a total amount of data transactions is below a predetermined level,

wherein if the total amount of data transactions is equal or above the predetermined level, the method further comprises

determining whether an amount of read transactions and an amount of write transactions in the period are approximately equal;

if the amount of read transactions is approximately equal to the amount of write transactions, selecting the second burst length; and

if the amount if read transactions is not approximately equal to the amount of write transactions, selecting the first burst length.

2. The method of claim 1 wherein determining whether an amount of read transactions and an amount of write transactions in the period are approximately equal comprises:

incrementing a count for each write transaction;

decrementing a count for each read transaction; and

determining whether the absolute value of the count is less than a threshhold.

3. The method of claim 2 wherein the memory controller is selected from the group comprising:

a DRAM controller;

a processor controller; and

a peripheral device controller.

4. A computer readable medium having instructions which, when executed by a processing system, cause the system to perform a method, the method comprising:

monitoring data traffic through a memory controller;

dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic, the burst length including a first burst length and a second burst length; and

selecting the first burst length if a total amount of data transactions is below a predetermined level,

wherein if the total amount of data transactions is equal or above the predetermined level, the method further comprises

determining whether an amount of read transactions and an amount of write transactions in the period are approximately equal;

if the amount of read transactions is approximately equal to the amount of write transactions, selecting the second burst length; and

if the amount if read transactions is not approximately equal to the amount of write transactions, selecting the first burst length.

5. The medium of claim 4 wherein the instructions, when executed, determine whether an amount of read transactions and an amount of write transactions in the period are approximately equal by:

incrementing a count for each write transaction;

decrementing a count for each read transaction; and

determining whether the absolute value of the count is less than a threshhold.

6. The medium of claim 5 wherein the memory controller is selected from the group comprising;

a DRAM controller;

a processor controller; and

a peripheral device controller.

7. An apparatus, comprising:

means for monitoring data traffic through a memory controller;

means for dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic, the burst length including a first burst length and a second burst length; and

means for selecting the first burst length if a total amount of data transactions is below a predetermined level,

wherein if the total amount of data transactions is equal or above the predetermined level, the apparatus further comprises

means for determining whether an amount of read transactions and an amount of write transactions in the period are approximately equal;

means for selecting the second burst length if the amount of read transactions is approximately equal to the amount of write transactions; and

means for selecting the first burst length if the amount if read transactions is not approximately equal to the amount of write transactions.

8. The apparatus of claim 7 wherein said means for determining whether an amount of read transactions and an amount of write transactions in the period are approximately equal comprises:

means for incrementing a count for each write transaction;

means for decrementing a count for each read transaction; and

means for determining whether the absolute value of the count is less than a threshhold.

9. An apparatus comprising:

a sampling period register to determine a period;

a saturating counter to count in response to read and write transactions in the period;

a comparator to provide an output indicating whether the read and write transactions in the period are approximately equal; and

a burst length policy register to receive the output of the comparator and to generate a burst length policy enable signal in response to the output of the comparator.

10. The apparatus of claim 9 wherein:

the burst length policy enable signal has a first state associated with a first burst length, and a second state associated with a second burst length, wherein the bandwidth of the first burst length is smaller than the second burst length.

11. The apparatus of claim 10 further comprising:

a first burst length value register having a first value associated with the first burst length to output the first value when enabled;

a second burst length value register having a second value associated with the second burst length to output the second value when enabled; and

a multiplexer to receive the burst length policy enable signal and to enable either the first burst length value register or the second burst length register in response to the burst length policy enable signal.