Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution

• US 6,615,343 B1
• Filed: 06/22/2000
• Issued: 09/02/2003
• Est. Priority Date: 06/22/2000
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Patel, Sanjay, Liebholz, Daniel L., Larson, Richard H., Talcott, Adam R.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US09/599,227
• Time in Patent Office: 1,167 Days
• Field of Search: 712/244, 710/260, 710/262
• US Class Current: 712/244
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set, and based on a class of the exception, processing the exception differently before signaling the trap. The method may include replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception. The method may include replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction. The method may include signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction. The method may include marking an instruction causing the exception as complete without issuing the instruction causing the exception. An apparatus for handling exceptions in a processor includes an instruction scheduler for setting a state upon detection of an exception and signaling a trap for the exception if the state is set. The instruction scheduler, based on a class of the exception, processes the exception differently before signaling the trap.

Claims

1. A method of handling an exception in a processor comprising:

setting a state upon detection of an exception;

signaling a trap for the exception if the state is set; and

based on a class of the exception, processing the exception differently before signaling the trap.

2. The method of claim 1 further comprising:

replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception.

3. The method of claim 2 further comprising:

replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction.

4. The method of claim 1 further comprising:

signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction.

5. The method of claim 1 further comprising:

marking an instruction causing the exception as complete without issuing the instruction causing the exception.

6. An apparatus for handling exceptions in a processor comprising:

an instruction scheduler for

setting a state upon detection of an exception; and

for signaling a trap for the exception if the state is set; and

wherein the instruction scheduler, based on a class of the exception, processes the exception differently before signaling the trap.

7. The apparatus of claim 6 wherein the instruction scheduler is further for

replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception.

8. The apparatus of claim 7 wherein the instruction scheduler is further for

replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction.

9. The apparatus of claim 6 wherein the instruction scheduler is further for

signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction.

10. The apparatus of claim 6 wherein the instruction scheduler is further for

marking an instruction causing the exception as complete without issuing the instruction causing the exception.

11. An apparatus for handling exceptions in a processor comprising:

means for setting a state upon detection of an exception;

means for signaling a trap for the exception if the state is set; and

means for processing the exception differently based on a class of the exception before the signaling of the trap.