Microprocessor with dual execution core operable in high reliability mode

• US 6,615,366 B1
• Filed: 12/21/1999
• Issued: 09/02/2003
• Est. Priority Date: 12/21/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rabago, Andres, Nguyen, Hang, Quach, Nhon, Grochowski, Edward T., Rash, William
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): McCarthy, Christopher
• Application Number:
  US09/470,096
• Time in Patent Office: 1,351 Days
• Field of Search: 714/11, 714/43, 714/12, 714/17, 714/10, 712/229, 712/20, 712/43, 700/4, 700/5
• US Class Current: 714/10
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to the type of code segment to be executed. When the processor is in high performance mode, the dual execution cores operate in lock step on identical instructions, and the execution results generated by each execution core are compared to detect any errors. In high performance monde, the dual execution cores operate independently.

Claims

1. A processor comprising:

first and second execution cores to process identical instructions in lock step when in a high reliability mode and to process instructions independently when in a high performance mode, the first and second execution cores being capable of switching between the high reliability and the high performance mode under software control.

2. The processor of claim 1, further comprising a check unit to compare execution results from the first and second execution cores when in the high reliability mode and signal an error when the execution results do not match.

3. The processor of claim 2, wherein the check unit is deactivated when in the high performance mode.

4. The processor of claim 2, further comprising a retirement unit, the retirement unit to retire an execution result from the first execution core when in the high reliability mode and the check unit does not signal an error.

5. The processor of claim 4, wherein the retirement unit retires execution results from the first and second execution cores when in the high performance mode and no exceptions are raised.

6. The processor of claim 1, wherein each of the execution cores enters a ready state when it executes a first mode switch instruction, the mode switch instruction switches the first and second execution cores to high reliability mode when both the first and second execution cores are in the ready state.

7. The processor of claim 1, wherein the first and second execution cores include first and second mode status bits, respectively, to indicate states of the first and second execution cores.

8. The processor of claim 7, wherein the first and second execution cores include first and second fetch stages, respectively, the first and second fetch states operate in a high reliability mode when the first and second mode status bits are in a first logic state.

9. The processor of claim 8, wherein the first fetch stage operates in high performance modes when the first mode status bit is in a second logic state, and the second fetch stage operates in high performance mode when the second mode status bit is in a second logic state.

10. The processor of claim 7, further comprising a check unit, the check unit being activated when the first and second mode status bits are in the first logic state, and the check unit being deactivated when either the first or second mode status bit is in the second logic state.

11. A computer system comprising:

a memory to store a plurality of instructions, including a mode switch instruction; and

a processor including first and second execution cores that operate in lock step when the processor is in a first mode and that operate independently when the processor is in a second mode, the processor switching between the first and second processor modes in response to the mode switch instruction.

12. The computer system of claim 11, wherein the processor further comprises a check unit that compares execution results generated by the first and second execution cores when the processor is in the first mode and signals an error if the execution results do not agree.

13. The computer system of claim 12, wherein the check unit is deactivated when the processor is in the second mode.

14. The computer system of claim 11, wherein the first and second execution cores include first and second fetch units, respectively, which fetch the same instruction from the memory when the processor is in the first mode and which fetch instructions from memory independently when the processor is in the second mode.

15. The computer system of claim 11, wherein the plurality of instructions includes instructions from a first code segment to be executed in the first mode and a second code segment to be executed in the second mode.

16. The computer system of claim 11, wherein the mode switch instruction comprises a first mode switch instruction to switch the processor from the first mode to the second mode and a second mode switch instruction to switch the processor from the second mode to the first mode.

17. A method for processing code segments in a dual core processor, the method comprising:

detecting a first code segment to be executed in high reliability mode;

executing a first mode switch instruction to place the processor in high reliability mode; and

executing the first code segment in high reliability mode, including first and second execution cores of the dual core processor processing identical instructions in lock step during the high reliability mode.

18. The method of claim 17, further comprising:

detecting a code segment to be executed in high performance mode;

executing a second mode switch instruction to switch the processor to high performance mode; and

executing the code segment in high performance mode.

19. The method of claim 17, wherein executing a first mode switch instruction comprises:

executing the first mode switch instruction on each of the dual execution cores to put each of the execution cores into a ready state; and

switching the processor to high reliability mode when each of the dual execution cores is in the ready state.

20. The method of claim 19, wherein executing the first mode switch instruction on each of the dual execution cores causes each of the dual execution core to:

save an architectural state for a currently executing code segment;

flush instructions from the execution core; and

initialize the execution for the first code segment.

21. A method for changing execution mode in a dual core processor, the method comprising:

switching a first execution core of the processor to a ready state;

switching a second execution core of the processor to the ready state;

switching the processor to a high reliability mode when the first and second execution cores are in the ready state, and

first and second execution cores of the dual core processor processing identical instructions in lock step during the high reliability mode.

22. The method of claim 21, wherein switching the first execution core comprises:

detecting a mode switch instruction;

setting a mode status bit to a first logic state; and

flushing an instruction pipeline associated with the execution core.

23. The method of claim 21, further comprising:

detecting a code segment to be processed in the high reliability mode; and

scheduling first and second mode switch instructions on the first and second execution cores when the processor is not already in the high reliability mode.

24. The method of claim 23, further comprising:

executing the code segment in the high reliability mode;

comparing execution results generated by the first and second execution cores; and

signaling an error when the execution results do not match.