Iterative decoder and an iterative decoding method for a communication system

• US 6,615,385 B1
• Filed: 12/30/1999
• Issued: 09/02/2003
• Est. Priority Date: 12/31/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Goo, Lee, Young-Hwan, Choi, Soon-Jae, Kim, Beong-Jo
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/475,684
• Time in Patent Office: 1,342 Days
• Field of Search: 714/795, 714/796, 714/794, 714/758
• US Class Current: 714/758
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2975 Judging correct decoding, e.g. iteration stopping criteria

Abstract

An iterative decoder and iterative decoding method. In the iterative decoder, a first adder has a first port for receiving information symbols and a second port. A first component decoder which is coupled to the first adder, receives first parity symbols and decodes the information symbols using first parity symbols and an output signal of the first adder. A first subtractor has a third port for receiving the output of the first component decoder, and a fourth port. An interleaver which is coupled to the output of the first subtractor, interleaves the decoded information symbols received from the first component decoder. A second component decoder receives the output of the interleaver and second parity symbols and decodes the information symbols of the interleaver output using the received signals. A deinterleaver deinterleaves the output of the second component decoder. A second subtractor has a fifth port for receiving the output of the deinterleaver and a sixth port for receiving an inverted output of the first subtractor. The output of the second subtractor is connected to the second port and an inverted output of the second subtractor is connected to the fourth port. A hard decision device converts the decoded symbols received from the first component decoder to binary information bits. An error detector checks errors in the binary information bits received from the hard decision device and generates a no error signal if no errors are detected. An output buffer stores the binary information bits received from the hard decision device and outputs the stored binary information bits in response to the no error signal.

Claims

1. An iterative decoder comprising:

a first adder having a first port for receiving information symbols and a second port for receiving an extrinsic information signal EXT2;

a first component decoder for receiving first parity symbols, and for decoding the information symbols using the first parity symbols and an output signal of the first adder;

a first subtractor having a third port for receiving an output of the first component decoder, and a fourth port for receiving an inverted signal of the extrinsic information signal EXT2;

an interleaver coupled to an output of the first subtractor, for interleaving the decoded information symbols received from the first component decoder;

a second component decoder for receiving an output of the interleaver and second parity symbols, and for decoding the information symbols from the interleaver output using the received signals;

a deinterleaver for deinterleaving an output of the second component decoder;

a second subtractor having a fifth port for receiving an output of the deinterleaver and a sixth port for receiving an inverted output of the first subtractor, said second subtractor having output to the second port and inverted output to the fourth port;

a hard decision device for converting output received from the first component decoder to binary information bits by hard decision decoding;

an error detector for checking for errors in the binary information bits received from the hard decision device and for generating a no error signal if no errors are detected; and

an output buffer for storing the binary information bits received from the hard decision device and for outputting the stored binary information bits in response to the no error signal.

2. The iterative decoder of claim 1, wherein the first and second component decoders are operated in a continuous mode.

3. The iterative decoder of claim 1, wherein the error detector a CRC (Cyclic Redundancy Check) error checker.

4. An iterative decoding device having a predetermined maximum number of iterations, comprising:

a first component decoder, for receiving information symbols and first parity symbols, and for decoding the information symbols using the first parity symbols;

an interleaver, coupled to the first component decoder, for interleaving an order of the first decoded information symbols from an original data order;

a second component decoder, for receiving an output of the interleaver and second parity symbols, and for decoding the information symbols output from the interleaver using the second parity symbols;

a deinterleaver for deinterleaving the second decoded information symbols to recover the original data order of the information symbols; and

an err detector for detecting errors in a decoded frame when the information symbols of the decoded frame are in the original data order;

wherein an output signal of the deinterleaver is fed back to the first decoder for iterative decoding, and wherein the decoded frame data is checked for errors, and, if there are no errors, the iterative decoding is stopped even though the predetermined number of iterations are not completed.

5. The iterative decoding device of claim 4, wherein the decoded frame data is received from the output of the first component decoder.

6. The iterative decoding device of claim 4, wherein the decoded frame data is received from the output of the deinterleaver.

7. The iterative decoding device of claim 4, wherein the iterative decoder further comprises:

first adder having a first port for receiving the information symbols, a second port for receiving an extrinsic information signal EXT2, and an output connected to the first component decoder;

a first subtractor having a third port for receiving an output of the first component decoder;

a fourth port for receiving an inverted signal of the extrinsic information signal EXT2, and an output connected to the interleaver; and

a second subtractor having a fifth port for receiving an output of the deinterleaver, a sixth port for receiving an inverted output of the first subtractor, and an output for outputting said extrinsic information signal EXT2.

8. The iterative decoding device of claim 7, wherein the error detector performs error detection on the output of the first component decoder.

9. The iterative decoding device of claim 7, wherein the first and second component decoders are operated in a continuous mode.

10. The iterative decoding device of claim 7, wherein the error detector is a Cyclic Redundancy Check (CRC) error checker.

11. The iterative decoding device of claim 7, wherein the error detector performs error detection on the output of the deinterleaver.

12. The iterative decoding device of claim 7, wherein the error detector receives the output of one of the first component decoder and the deinterleaver, and performs error detection on the output.

13. An iterative decoding method for an iterative decoder having a predetermined maximum number of iterations, comprising the steps of:

receiving information symbols and first parity symbols and performing first decoding on the information symbols using the first parity symbols;

interleaving an order of the information symbols which are first decoded with the first parity symbols from an original data order;

receiving the interleaved information symbols of which the original data order is changed and second parity symbols, and performing second decoding on the interleaved information symbols using the second parity symbols;

deinterleaving the information symbols which are second decoded with the second parity symbols to recover the original data order of the information symbols;

checking for errors on a decoded frame as the information symbols are recovered into the original final data order before the predetermined number of iterations are completed; and

stopping, even though the predetermined number of iterations are not completed, the iterative decoding whenever there are no error in the decoded frame,

wherein the deinterleaved signal is fed back to the first decoding step for iterative decoding.

14. The iterative decoding method of claim 13, wherein the decoded frame is achieved from the first decoding step.

15. The iterative decoding method of claim 13, wherein the decoded frame is achieved from the deinterleaving step.

16. The iterative decoding method of claim 13, wherein the step of iteratively decoding further comprises:

adding the information symbols and an extrinsic information signal EXT2; and

subtracting the first-decoded information symbols and an inverted signal of the extrinsic information signal EXT2.

17. The iterative decoding method of claim 16, wherein the error checking is performed on the output of the first decoded information symbols.

18. The iterative method of claim 16, wherein the first and second decoding is operated in a continuous mode.

19. The iterative decoding method of claim 16, wherein the error checking is performed using a Cyclic Redundancy Check (CRC) error.

20. The iterative decoding method of claim 16, wherein the error checking is performed on the deinterleaved information symbols.