Semiconductor device and semiconductor substrate, and method for fabricating the same

• US 6,617,182 B2
• Filed: 09/14/1999
• Issued: 09/09/2003
• Est. Priority Date: 09/14/1998
• Status: Expired due to Term

• Current Assignee: Xiamen San'An Optoelectronics Co.Ltd. (Sanan Optoelectronics Company Limited)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ishida, Masahiro, Yuri, Masaaki, Nakamura, Shinji, Orita, Kenji, Imafuji, Osamu
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US09/395,261
• Publication Number:
  US 20020137249A1
• Time in Patent Office: 1,456 Days
• Field of Search: 438/22, 438/46, 438/47, 438/478, 438/479, 438/481, 438/483, 438/40, 438/41, 438/43, 438/44, 438/700, 438/705, 438/706, 438/718
• US Class Current: 438/22
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

A semiconductor device includes: a crystalline substrate including a primary surface and a crystal plane provided within the primary surface so as to have a surface orientation different from a surface orientation of the primary surface; a semiconductor layered structure grown over the crystalline substrate; and an active region provided at a portion in the semiconductor layer structure above the crystal plane.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of:

forming a crystal plane on a primary surface of a substrate of a III group nitride compound material to provide a stepped portion so that a surface orientation of the crystal plane is different from a surface orientation of the primary surface of the substrate;

wherein the primary surface is in a convex configuration with respect to the crystal plane;

wherein the crystal plane forming step includes the steps of forming a mask having a predetermined pattern on the substrate, selectively etching a portion of the substrate not covered with the mask, and removing the mask; and

forming a semiconductor layered structure made of a III group nitride compound material directly on both the crystal plane and the primary surface of the substrate, wherein the crystal plane is formed so as to be a tilted surface with respect to the primary surface, whereby a low-defect region in the semiconductor layered structure is provided containing fewer defects as compared to surrounding regions.

2. A method according to claim 1, wherein the substrate is made of Al_xGa_1-xN (0≦

x≦

1), and the semiconductor layered structure forming step includes the step of forming an Al_yGa_1-yN layer (0≦

y≦

1) at a crystal growth temperature of about 900°

C. or more.

3. A method according to claim 1, wherein the semiconductor layered structure forming step includes the steps of:

forming over the substrate, a first Al_aGa_1-aN layer (0≦

a≦

1) at a crystal growth temperature in a range of about 400°

C. to about 900°

C.; and

forming Over the first Al_aGa_1-aN layer, a second Al_aGa_1-aN layer (0≦

b≦

1) at a crystal growth temperature of about 900°

C. or more.

4. A method according to claim 1, wherein the semiconductor layered structure forming step includes the step of introducing an impurity to a predetermined portion of the semiconductor layered structure at a concentration of about 10²¹ cm⁻

3 or less.

5. A method according to claim 1, wherein in the semiconductor layered structure forming step, a mole supply ratio of a V group source material to a III group source material (a V/III ratio) is about 200 or more.

11. A method according claim 1, further comprising the step separating the semiconductor layer from the substrate.

12. A method according to claim 11, wherein the crystal plane provided within the primary surface of the substrate extends along a <

1,1,−

2,0>

direction.

13. A method according to claim 1, wherein a crystal growth direction of the substrate is oriented toward a tilted direction in accordance with the tilt of the stepped portion of the substrate.

15. A method according to claim 11, wherein a crystal growth direction of the substrate is oriented toward a tilted direction in accordance with the tilt of the stepped portion of the substrate.

16. A method according to claim 1, 6 or 11, wherein the crystal plane forming step includes the step of heating the substrate.

6. A method for fabricating a semiconductor device, comprising the steps of:

forming a first crystal plane on a primary surface of a substrate of a III group nitride compound material to provide a stepped portion so that a surface orientation of the first crystal plane is different from a surface orientation of the primary surface of the substrate;

wherein the primary surface is in a convex configuration with respect to the first crystal plane;

wherein the first crystal plane forming step includes the steps of forming a mask having a predetermined pattern on the substrate, selectively etching a portion of the substrate not covered with the mask, and removing the mask;

forming a first semiconductor layer directly on both the first crystal plane and the primary surface of the substrate;

forming a second crystal plane on a primary surface of the first semiconductor layer so that a surface orientation of the second crystal plane is different from a surface orientation of the primary surface of the first semiconductor layer;

wherein the primary surface of the first semiconductor layer is in a convex configuration with respect to the second crystal plane;

wherein the second crystal plane forming step includes the steps of forming a mask having a predetermined pattern on the first semiconductor layer, selectively etching a portion of the first semiconductor layer not covered with the mask, and removing the mask; and

forming a second semiconductor layer made of a III group nitride compound material directly on both the second crystal plane and the primary surface of the first semiconductor layer, wherein the first crystal plane is formed so as to be a tilted surface with respect to the primary surface of the substrate and the second crystal plane is formed so as to be a tilted surface with respect to the primary surface of the first semiconductor layer, whereby low-defect regions in the first and second semiconductor layers are provided containing fewer defects as compared to surrounding regions.

7. A method according to claim 6, wherein the substrate is made of Al_xGa_1-xN (0≦

x≦

1), and the second semiconductor layer forming step includes the step of forming an Al_yGa_1-yN layer (0≦

y≦

1) at a crystal growth temperature of about 900°

C. or more.

8. A method according to claim 6, wherein the second semiconductor layer forming step includes the steps of:

forming over the substrate, a Al₈Ga_1-aN buffer layer (0≦

a≦

1) at a crystal growth temperature in a range of about 400°

C. to about 900°

C.; and

forming over the Al_aGa_1-aN buffer layer, a second Al_bGa_1-bN layer (0≦

b≦

1) at a crystal growth temperature of about 900°

C. or more.

9. A method according to claim 6, wherein the second semiconductor layer forming step includes the step of introducing an impurity to the second semiconductor layer at a concentration of about 10²¹ cm⁻

3 or less.

10. A method according to claim 6, wherein in the second semiconductor layer forming step, a mole supply ratio of a V group source material to a III group source material (a V/III ratio) is about 200 or more.

14. A method according to claim 6, wherein a crystal growth direction of the substrate is oriented toward a tilted direction in accordance with the tilt of the stepped portion of the substrate.