Multi-layered gate for a CMOS imager
First Claim
Patent Images
1. A CMOS imager comprising:
- an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises at least two gates, wherein one of said at least two gates comprises a semi-transparent conductive layer formed to at least partially overlap another of said at least two gates; and
a circuit electrically connected to receive and process output signals from said array.
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Abstract
A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.
184 Citations
20 Claims
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1. A CMOS imager comprising:
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an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises at least two gates, wherein one of said at least two gates comprises a semi-transparent conductive layer formed to at least partially overlap another of said at least two gates; and
a circuit electrically connected to receive and process output signals from said array. - View Dependent Claims (2, 3, 4, 5)
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6. A CMOS imager comprising:
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an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises a first gate stack, a second gate, said second gate separated from said first gate stack by an insulating layer and comprising a semi-transparent conductive layer formed to at least partially overlap the first gate stack, and a floating diffusion region; and
a circuit electrically connected to receive and process output signals from said array. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. An imager comprising:
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a CMOS imager, said CMOS imager comprising an array of pixel sensor cells formed in a photosensitive region on a substrate, wherein at least one of said pixel sensor cells comprises at least two gates, wherein one of said at least two gates comprises a semi-transparent conductive layer formed to at least partially overlap another of said at least two gates, and a circuit formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and
a central processing unit for receiving and processing data representing said image. - View Dependent Claims (16, 17)
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18. A CMOS imager comprising:
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an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises;
a photosensitive region of a first conductivity type formed on a substrate;
a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;
a first insulating layer formed over said substrate;
a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer over a first portion of said first insulating layer, a second insulating layer over the first conductive layer, and insulating spacers for defining structure in said substrate, said insulating spacers being formed on the sides of said first gate; and
a second gate formed over a second portion of said first insulating layer, said second portion of said first insulating layer overlying said structure in said substrate, and said second gate comprising a semi-transparent conductive layer formed over said second insulating layer and extending at least partially over said first gate; and
a circuit electrically connected to receive and process output signals from said array.
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19. A CMOS imager comprising:
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an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises;
a photosensitive region of a first conductivity type formed in a substrate;
a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;
a first insulating layer formed over said substrate;
a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer over a first portion of said first insulating layer, a second insulating layer over the first conductive layer, and insulating spacers formed on the sides of said first gate; and
a second gate formed over a second portion of said first insulating layer, said second gate comprising a semi-transparent conductive layer formed over said first insulating layer and extending at least partially over said first gate; and
a circuit electrically connected to receive and process output signals from said array.
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20. An imager comprising:
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a CMOS imager, said CMOS imager comprising an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises;
a photosensitive region of a first conductivity type formed in a substrate;
a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;
a first insulating layer formed over said substrate;
a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer over a first portion of said first insulating layer, a second insulating layer formed over the first conductive layer, and insulating spacers formed on the sides of said first gate;
a second gate formed over a second portion of said second insulating layer, said second gate comprising a semi-transparent conductive layer formed over said second insulating layer and extending at least partially over said first gate;
a circuit formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and
a central processing unit for receiving and processing data representing said image.
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Specification