Multi-layered gate for a CMOS imager

• US 6,617,623 B2
• Filed: 04/12/2001
• Issued: 09/09/2003
• Est. Priority Date: 06/15/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/832,856
• Publication Number:
  US 20010022371A1
• Time in Patent Office: 880 Days
• Field of Search: 257/59, 257/72, 257/215, 257/290-292
• US Class Current: 257/215
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Claims

1. A CMOS imager comprising:

an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises at least two gates, wherein one of said at least two gates comprises a semi-transparent conductive layer formed to at least partially overlap another of said at least two gates; and

a circuit electrically connected to receive and process output signals from said array.

2. The CMOS imager of claim 1, wherein one of said at least two gates comprises a photogate formed to at least partially overlap a transfer gate.

3. The CMOS imager of claim 1, wherein one of said at least two gates comprises a transfer gate formed to at least partially overlap a photogate.

4. The CMOS imager of claim 1, wherein one of said at least two gates comprises a source follower gate formed to at least partially overlap a row select gate.

5. The CMOS imager of claim 1, wherein one of said at least two gates comprises a row select gate formed to at least partially overlap a source follower gate.

6. A CMOS imager comprising:

an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises a first gate stack, a second gate, said second gate separated from said first gate stack by an insulating layer and comprising a semi-transparent conductive layer formed to at least partially overlap the first gate stack, and a floating diffusion region; and

a circuit electrically connected to receive and process output signals from said array.

7. The CMOS imager of claim 6, wherein the first gate stacks comprise a first insulating layer, and a conductive layer on the first insulating layer.

8. The CMOS imager of claim 6, wherein the second gates comprise a second insulating layer, and a second conductive layer on the second insulating layer.

9. The CMOS imager of claim 6, wherein the first gate is a transfer gate and the second gate is a photogate.

10. The CMOS imager of claim 6, wherein the first gate is a photogate and the second gate is a transfer gate.

11. The CMOS image of claim 6, wherein the first gate is a source follower gate, and the second gate is a row select gate.

12. The CMOS imager of claim 6, wherein the first gate is a row select gate, and the second gate is a source follower gate.

13. The CMOS imager of claim 6, wherein each pixel sensor cell further comprises a reset transistor for periodically resetting a charge level of the floating diffusion region.

14. The CMOS imager of claim 6, wherein each pixel sensor cell comprises an output transistor having a gate electrically connected to the floating diffusion region.

15. An imager comprising:

a CMOS imager, said CMOS imager comprising an array of pixel sensor cells formed in a photosensitive region on a substrate, wherein at least one of said pixel sensor cells comprises at least two gates, wherein one of said at least two gates comprises a semi-transparent conductive layer formed to at least partially overlap another of said at least two gates, and a circuit formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and

a central processing unit for receiving and processing data representing said image.

16. The imager of claim 15, wherein said array, said circuit, and said central processing unit are formed on a single substrate.

17. The imager of claim 15, wherein said array and said circuit are formed on a first substrate and said central processing unit is formed on a second substrate.

18. A CMOS imager comprising:

an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises;

a photosensitive region of a first conductivity type formed on a substrate;

a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;

a first insulating layer formed over said substrate;

a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer over a first portion of said first insulating layer, a second insulating layer over the first conductive layer, and insulating spacers for defining structure in said substrate, said insulating spacers being formed on the sides of said first gate; and

a second gate formed over a second portion of said first insulating layer, said second portion of said first insulating layer overlying said structure in said substrate, and said second gate comprising a semi-transparent conductive layer formed over said second insulating layer and extending at least partially over said first gate; and

a circuit electrically connected to receive and process output signals from said array.

19. A CMOS imager comprising:

an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises;

a photosensitive region of a first conductivity type formed in a substrate;

a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;

a first insulating layer formed over said substrate;

a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer over a first portion of said first insulating layer, a second insulating layer over the first conductive layer, and insulating spacers formed on the sides of said first gate; and

a second gate formed over a second portion of said first insulating layer, said second gate comprising a semi-transparent conductive layer formed over said first insulating layer and extending at least partially over said first gate; and

a circuit electrically connected to receive and process output signals from said array.

20. An imager comprising:

a CMOS imager, said CMOS imager comprising an array of pixel sensor cells, wherein at least one of said pixel sensor cells comprises;

a photosensitive region of a first conductivity type formed in a substrate;

a floating diffusion region of a second conductivity type formed in the substrate and spaced from said photosensitive region;

a first insulating layer formed over said substrate;

a first gate formed on said first insulating layer over said photosensitive region, said first gate comprising a first conductive layer over a first portion of said first insulating layer, a second insulating layer formed over the first conductive layer, and insulating spacers formed on the sides of said first gate;

a second gate formed over a second portion of said second insulating layer, said second gate comprising a semi-transparent conductive layer formed over said second insulating layer and extending at least partially over said first gate;

a circuit formed in said substrate and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image; and

a central processing unit for receiving and processing data representing said image.