Semiconductor device and a method of manufacturing the same

• US 6,617,632 B2
• Filed: 12/07/2001
• Issued: 09/09/2003
• Est. Priority Date: 12/19/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Takada, Hidenori, Matsuzaki, Nozomu, Kume, Hitoshi, Shiba, Kazuyoshi, Shukuri, Shoji, Taniguchi, Yasuhiro
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/005,300
• Publication Number:
  US 20020074569A1
• Time in Patent Office: 641 Days
• Field of Search: 257/317, 257/330, 257/364, 257/407
• US Class Current: 257/296
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-through stopper layer which is adjacent to the first semiconductor region and formed by introducing a first conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially higher than the channel region in impurity concentration, and wherein the source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns, word lines some of which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and when carriers are stored in a floating gate electrode of each selected memory cell, a negative voltage is applied to other non-selected word lines other than the selected word line.

Claims

1. A semiconductor device comprising:

a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including,

a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed;

source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;

a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of the second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and

a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region,

wherein the control gate electrode is electrically connected to its corresponding word line, and a negative voltage is applied to each non-selected word line upon a write operation.

2. The semiconductor device according to claim 1, wherein the impurity of the second conductivity type, which constitutes the first semiconductor region, is phosphorus.

3. The semiconductor device according to claim 1, wherein storage of the carriers in the floating gate electrode of the nonvolatile memory cell is carried out by hot-electron injection of electrons having obtained high energy in the neighborhood of the end of the drain region into the floating gate electrode.

4. The semiconductor device according to claim 1, wherein discharge of carriers from the floating gate electrode of the nonvolatile memory cell is carried out by tunnel emission of the electrons in the floating gate electrode into the semiconductor substrate.

5. The semiconductor device according to claim 1, further including a third semiconductor region which is adjacent to the source region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the source side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region.

6. The semiconductor device according to claim 1, wherein the source and drain regions comprise a low-concentration semiconductor region of relatively low impurity concentration and a high-concentration semiconductor region of relatively high impurity concentration, and the first semiconductor region, the low-concentration semiconductor region, and the high-concentration semiconductor region are formed in order from the side that faces the channel region.

7. A semiconductor device comprising:

a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including,

a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed;

source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;

a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of a second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and

a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region,

wherein the source and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns,

wherein word lines which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows,

wherein a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and

wherein when carriers are stored in a floating gate electrode of a nonvolatile memory cell connected to the selected word line, a negative voltage is applied to other non-selected word lines other than the selected word line.

8. The semiconductor device according to claim 7, wherein the impurity of the second conductivity type, which constitutes the first semiconductor region, is phosphorus.

9. The semiconductor device according to claim 7, wherein the storage of the carriers in the floating gate electrode of the nonvolatile memory cell is carried out by hot-electron injection of electrons having obtained high energy in the neighborhood of the end of the drain region into the floating gate electrode.

10. The semiconductor device according to claim 7, wherein the discharge of carriers from the floating gate electrode of the nonvolatile memory cell is carried out by tunnel emission of the electrons in the floating gate electrode into the semiconductor substrate.

11. The semiconductor device according to claim 7, further including a third semiconductor region which is adjacent to the source region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the source side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region.

12. The semiconductor device according to claim 7, wherein the source and drain regions comprise a low-concentration semiconductor region of relatively low impurity concentration and a high-concentration semiconductor region of relatively high impurity concentration, and the first semiconductor region, the low-concentration semiconductor region, and the high-concentration semiconductor region are formed in order from the side that faces the channel region.

13. A semiconductor device comprising:

a plurality of nonvolatile memory cells arranged on a semiconductor substrate in matrix form, each including

a gate insulating film covering a channel region in a main surface of the semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode successively formed;

source and drain regions of a second conductivity type formed in the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween;

a first semiconductor region which is adjacent to the drain region and formed by introducing an impurity of the second conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively lower than that of the drain region; and

a second semiconductor region which is adjacent to the first semiconductor region and formed by introducing an impurity of the first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region,

wherein the control gate electrode is electrically connected to a corresponding word line, and a negative voltage is applied to each non-selected word line upon a write operation,

wherein storage of the carriers in the floating gate electrode of the nonvolatile memory cell is carried out by hot-electron injection of electrons having obtained high energy in the neighborhood of the end of the drain region into the floating gate electrode, and

wherein the source and drain regions comprise a low-concentration semiconductor region of relatively low impurity concentration and a high-concentration semiconductor region of relatively high impurity concentration, and the first semiconductor region, the low-concentration semiconductor region, and the high-concentration semiconductor region are formed in order from the side that faces the channel region.

14. The semiconductor device according to claim 13, wherein the impurity of the second conductivity type, which constitutes the first semiconductor region, is phosphorus.