Reduced cost, high speed integrated circuit test arrangement

• US 6,617,872 B2
• Filed: 01/14/2002
• Issued: 09/09/2003
• Est. Priority Date: 10/04/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Vogley, Wilbur C.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US10/047,877
• Publication Number:
  US 20020109523A1
• Time in Patent Office: 603 Days
• Field of Search: 324/158.1, 324/754, 324/755, 324/765, 702/117, 702/118, 702/119, 702/122, 702/123, 702/124, 702/188, 714/25, 714/46, 714/715, 714/718, 714/719, 714/720, 714/724, 714/728, 714/727, 714/738, 700/28, 700/32, 700/38, 700/39
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Claims

1. A method of testing comprising the steps of:

selecting a test algorithm at a control computer;

sending the test algorithm to a first plurality of integrated circuits;

executing the test algorithm at each of the plurality of integrated circuits;

producing a plurality of respective test signals at each integrated circuit of the first plurality of integrated circuits corresponding to the test algorithm;

applying the plurality of respective test signals to a respective second plurality of integrated circuits to be tested; and

testing each integrated circuit of the second plurality of integrated circuits in response to the plurality of respective test signals.

2. A method of testing as in claim 1 comprising the steps of:

sending the test algorithm to the plurality of integrated circuits on a serial bus; and

receiving respective test data on the serial bus from each of said circuits to be tested.

3. A method of testing as in claim 2, wherein the steps of sending and receiving correspond to a scalable coherent interface standard.

4. A method of testing as in claim 1, wherein at least one of the circuits to be tested comprises an analog circuit.

5. A method of testing as in claim 1, wherein the circuits to be tested comprise analog and memory circuits, and wherein the analog and memory circuits are tested simultaneously.

6. A method of testing as in claim 1, wherein the step of sending the test algorithm to a plurality of integrated circuits comprises sending packets of data, each packet of data having an address signal and a data signal, each address signal designating a specific integrated circuit of the plurality of integrated circuits to receive the data signal.

7. A method of testing as in claim 1, comprising the steps of:

selectively delaying test signals of the plurality of respective test signals by a predetermined time; and

applying the selectively delayed test signals to respective circuits to be tested at substantially the same time.

8. A method of testing as in claim 1, wherein the circuits to be tested are memory circuits, and wherein the respective test signals include address, data, and control signals.

9. A method as in claim 1, wherein the step of testing comprises modifying a power supply voltage applied to said each integrated circuit.

10. A method comprising the steps of:

selecting an algorithm at a control computer;

sending the algorithm to a plurality of integrated circuits;

executing the algorithm at each of the plurality of integrated circuits;

producing a plurality of respective address, data, and control signals at each integrated circuit corresponding to the algorithm, wherein the address signals include row and column address signals, and wherein the control signals include row and column control signals; and

applying the plurality of respective signals to respective operating circuits.

11. A method as in claim 10, wherein at least one of the operating circuits comprises an analog circuit.

12. A method as in claim 10, wherein the operating circuits comprise analog and memory circuits, and wherein the analog and memory circuits are operated simultaneously.

13. A method as in claim 10, wherein the step of sending the algorithm to a plurality of integrated circuits comprises sending packets of data, each packet of data having an address signal and a data signal, each address signal designating a specific integrated circuit of the plurality of integrated circuits to receive the data signal.

14. A method as in claim 10, comprising the steps of:

selectively delaying signals of the plurality of respective signals by a predetermined time; and

applying the selectively delayed signals to respective operating circuits at substantially the same time.

15. A method as in claim 10, comprising the steps of:

producing a power supply voltage at the respective operating circuits; and

modifying the power supply voltage.

16. A method comprising the steps of:

selecting an algorithm at a control computer;

sending the algorithm to a plurality of integrated circuits;

sending the algorithm to the plurality of integrated circuits on a serial bus;

executing the algorithm at each of the plurality of integrated circuits;

producing a plurality of respective signals at each integrated circuit corresponding to the algorithm;

applying the plurality of respective signals to respective operating circuits; and

receiving respective data on the serial bus from each of said operating circuits, wherein the steps of sending and receiving correspond to a scalable coherent interface standard.

17. A method as in claim 16, comprising the steps of:

producing a power supply voltage at said each integrated circuit; and

modifying the power supply voltage.