Transparently partitioned communication bus for multi-port bridge for a local area network
First Claim
1. An apparatus having a partitioned bus for transferring data, the apparatus comprising:
- a. a first bus segment having a first plurality of (n) signal lines;
b. a second bus segment having a second plurality of (n) signal lines;
c. conditioning means coupled to the first bus segment for conditioning a logic level of each signal line of the first bus segment according to data to be transferred;
d. sensing means coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment;
e. pre-charging means coupled to the second bus segment for pre-charging each signal line of the second bus segment; and
f. dis-charging means coupled to the second bus segment for dis-charging selected ones of the signal lines of the second bus segment so as to replicate logic levels of the corresponding signal lines of the first bus segment.
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Accused Products
Abstract
A transparently partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network. The communication bus is partitioned into a plurality of bus segments, each segment coupled to one or more ports of the multi-port bridge and including a same number (n) of signal lines. A controller pre-charges each signal line to a logic high voltage level by activating pre-charge transistors coupled between a voltage supply and a plurality of diodes, each diode coupled to a corresponding one of the signal lines. The pre-charging operation includes all the signal lines. The ports request access to the partitioned bus. A port having been granted access to the partitioned bus applies data to its associated bus segment. The transparent controller then senses the data applied by the port via sense lines. Then, the transparent controller replicates this data to each other bus segment by discharging appropriate ones of the signal lines of each other bus segment via appropriate ones of a plurality of discharge transistors. The discharge transistors are coupled to between each signal line and ground. This technique results in the data being quickly replicated to the other bus segments. Accordingly, the bus is “transparently” partitioned such that the bus segments, in conjunction with the controller, form a single logical bus by which the ports communicate data. A principle advantage is that the entire bus cycle can be made shorter than a bus cycle for a non-partitioned bus.
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Citations
29 Claims
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1. An apparatus having a partitioned bus for transferring data, the apparatus comprising:
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a. a first bus segment having a first plurality of (n) signal lines;
b. a second bus segment having a second plurality of (n) signal lines;
c. conditioning means coupled to the first bus segment for conditioning a logic level of each signal line of the first bus segment according to data to be transferred;
d. sensing means coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment;
e. pre-charging means coupled to the second bus segment for pre-charging each signal line of the second bus segment; and
f. dis-charging means coupled to the second bus segment for dis-charging selected ones of the signal lines of the second bus segment so as to replicate logic levels of the corresponding signal lines of the first bus segment. - View Dependent Claims (2, 3, 4, 5)
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6. A multi-port bridge having a partitioned bus for transferring data between ports of the multi-port bridge, the multi-port bridge comprising:
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a. a first bus segment having a first plurality of (n) signal lines;
b. a second bus segment having a second plurality of (n) signal lines;
c. a controller coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment;
d. a transistor coupled to be controlled by the controller for pre-charging each signal line of the second bus segment; and
e. a plurality of transistors coupled to be controlled by the controller for dis-charging selected ones of the signal lines of the second bus segment so as to replicate logic levels of the corresponding signal lines of the first bus segment. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of transferring data between ports of a multi-port bridge, the method comprising steps of:
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a. conditioning a first bus segment having a first plurality of (n) signal lines according to logic levels of data to be transferred by a first port;
b. pre-charging a second bus segment having a second plurality of (n) signal lines whereby each signal line of each of the second bus segment attains a logic high voltage level;
c. sensing a logic level of each signal line of the first bus segment; and
d. dis-charging selected ones of the signal lines of the second bus segment to a logic low voltage level so as to replicate the logic levels of the first bus segment. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A multi-port bridge having a partitioned bus for transferring data between ports the multi-port bridge, the multi-port bridge comprising:
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a. a first bus segment having a first plurality of (n) signal lines;
b. a second bus segment having a second plurality of (n) signal lines;
c. a controller coupled to the first bus segment via a first plurality of (n) sense lines for sensing a respective logic level of each signal line of the first bus segment and coupled to the second bus segment via a second plurality of (n) sense lines for sensing a respective logic level of each signal line of the second bus segment;
d. a first plurality of diodes, each having an anode and a cathode, wherein the cathodes of the first plurality of diodes are each coupled to a respective one of the signal lines of the first bus segment and the anodes of the first plurality of diodes are each selectively coupled to a supply voltage under control of the controller;
e. a second plurality of diodes, each having an anode and a cathode, wherein the cathodes of the first plurality of diodes are each coupled to a respective one of the signal lines of the second bus segment and the anodes of the second plurality of diodes are each selectively coupled to a first supply voltage level under control of the controller;
f. a first plurality of transistors, each having an input terminal, an output terminal and a control terminal, wherein the input terminals of the first plurality of transistors are each coupled to a second supply voltage level, and wherein the output terminals of the first plurality of transistors are each coupled to a respective one of the signal lines of the first bus segment and further wherein the control terminals of the first plurality of transistors are each coupled to the controller; and
g. a second plurality of transistors, each having an input terminal, an output terminal and a control terminal, wherein the input terminals of the second plurality of transistors are each coupled to the second supply voltage level, and wherein the output terminals of the second plurality of transistors are each coupled to a respective one of the signal lines of the second bus segment and further wherein the control terminals of the second plurality of transistors are each coupled to the controller. - View Dependent Claims (25, 26, 27, 28, 29)
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Specification