Tail current node equalization for a variable offset amplifier
First Claim
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1. An amplifier circuit comprising:
- first and second differential pairs;
first and second variable current generators coupled to respective tail current nodes of the first and second differential pairs, to control respective tail currents of the first and second differential pairs; and
a switch circuit coupled to equalize the voltages of the respective tail current nodes.
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Abstract
First and second differential transistor pairs, where each may be intentionally unbalanced or balanced, are provided. First and second variable current generators are coupled to control respective tail currents of the first and second differential pairs. A switch circuit is coupled to equalize the voltages of the respective tail current nodes. Applications of the amplifier circuit include sense amplifiers and comparators.
40 Citations
30 Claims
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1. An amplifier circuit comprising:
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first and second differential pairs;
first and second variable current generators coupled to respective tail current nodes of the first and second differential pairs, to control respective tail currents of the first and second differential pairs; and
a switch circuit coupled to equalize the voltages of the respective tail current nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7)
a regenerative load circuit whose input is coupled to first and second output nodes of the first and second differential pairs.
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3. The amplifier circuit of claim 2 further comprising:
a further switch circuit coupled to equalize the voltages of the first and second output nodes of the first and second differential pairs.
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4. The amplifier circuit of claim 3 wherein a plurality of input nodes of the first and second differential pairs are connected to each other so that when a differential input signal is received at a pair of input nodes of the first differential pair, an inverse of that input signal is at a pair of input nodes of the second differential pair.
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5. The amplifier circuit of claim 4 wherein the first and second variable current generators are digitally controllable.
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6. The amplifier circuit of claim 1 wherein the transistors of each differential pair are intentionally mismatched, and wherein each differential pair has first and second output nodes, the first output node of the first pair being coupled to the second output node of the second pair, the second output node of the first pair being coupled to the first output node of the second pair.
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7. The amplifier circuit of claim 1 wherein the transistors of each differential pair are matched, and each pair having first and second transistors, the first transistors of each pair being coupled to a common input node, and the second transistors of each pair being coupled to further common input node, an output node of the amplifier being coupled to be driven by one but not both of the first and second transistors of one of the pairs, and not driven by the other pair.
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8. A circuit comprising:
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means for driving the voltages of first and second output nodes in opposite directions, in accordance with an input voltage difference, the driving means having an offset that is a function of first and second currents through respective first and second bias nodes of the driving means;
means for changing the first and second currents in accordance with a control input; and
means for reducing changes in the first and second currents, said changes being caused by noise injected into the first and second bias nodes. - View Dependent Claims (9, 10, 11)
means for regeneratively driving the first and second output nodes.
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10. The circuit of claim 9 further comprising:
means for equalizing the voltages of the first and second output nodes.
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11. The circuit of claim 8 further comprising:
means for improving the common mode rejection of the driving means as a function of the voltages of the first and second bias nodes.
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12. A circuit comprising:
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first and second pairs of source coupled transistors, the transistors of each pair being intentionally mismatched and connected to drive first and second output nodes;
a first variable current generator coupled to provide a current being one of (1) directed into, and (2) directed out of, a common source node of the first pair of transistors;
a second variable current generator coupled to provide a current being one of (1) directed into, and (2) directed out of, a common source node of the second pair of transistors; and
a switch circuit coupled to equalize the voltages of the common source nodes. - View Dependent Claims (13, 14, 15, 16, 17, 18)
a latch circuit whose input is coupled to the first and second output nodes.
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15. The circuit of claim 14 further comprising:
a further switch circuit coupled to equalize the voltages of the first and second output nodes.
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16. The circuit of claim 15 wherein an input node of the larger one of the first pair of transistors is shorted to an input node of the smaller one of the second pair of transistors, and an input node of a smaller one of the first pair of transistors is shorted to an input node of a larger one of the second pair of transistors.
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17. The circuit of claim 16 wherein the first and second variable current generators have digital control inputs.
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18. The circuit of claim 16 wherein the transistors of each pair have the same size ratio 1:
- N where N is a positive integer greater than one.
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19. A method for sensing a differential signal, comprising:
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equalizing voltages of tail current nodes of first and second differential pairs, that are coupled to drive first and second output nodes with a regenerative circuit; and
thenreleasing the tail current nodes of the first and second differential pairs, while a differential signal is being applied to first and second input nodes of the first and second differential pairs; and
thenevaluating the first and second output nodes. - View Dependent Claims (20, 21, 22, 23)
prior to equalizing the voltages of the tail current nodes, trimming an offset of the first and second differential pairs, by changing respective tail currents of the first and second differential pairs, while the first and second input nodes are equalized, until the first and second output nodes change to another discrete state.
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23. The method of claim 22 wherein the respective tail currents are changed by changing a binary variable which causes the tail currents to change in discrete, predetermined amounts.
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24. An article of manufacture comprising:
a machine-readable medium having data that when accessed by a processor causes a representation of a circuit that has a pair of differential amplifiers, a pair of variable current generators whose outputs are respective tail current nodes of the pair of differential amplifiers, and a switch circuit coupled to equalize the voltages of the tail current nodes. - View Dependent Claims (25, 26, 27)
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28. A system comprising:
first and second integrated circuit dies coupled to communicate with each other via a data communications bus, the bus being designed to carry a differential signal between the first and second dies, the first die having a bus interface in which an on-chip variable offset comparator has a pair of input nodes coupled to receive the differential signal, the comparator having a pair of differential amplifiers that have the input nodes, a pair of variable current generators whose outputs are respective tail current nodes of the pair of mismatched differential amplifiers, and a switch circuit coupled to equalize the voltages of the tail current nodes. - View Dependent Claims (29, 30)
Specification