Method and apparatus for biasing selected and unselected array lines when writing a memory array

• US 6,618,295 B2
• Filed: 06/29/2001
• Issued: 09/09/2003
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US09/897,771
• Publication Number:
  US 20020136047A1
• Time in Patent Office: 802 Days
• Field of Search: 365/185.23, 365/189.09, 365/230.06, 365/94
• US Class Current: 365/189.09
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A passive element memory array preferably biases selected X-lines to an externally received V_PP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to V_PP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The V_PP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip V_PP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Claims

1. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of writing a selected memory cell coupled between a selected X-line and a selected Y-line, said method comprising the steps of:

biasing the selected X-line to a first voltage;

biasing the selected Y-line to a second voltage different than the first voltage;

biasing at least some unselected X-lines to a third voltage within a range defined by the first and second voltages; and

biasing at least some unselected Y-lines to a fourth voltage within the range defined by the first and second voltages and substantially different than the first and second voltages.

2. A method as recited in claim 1 wherein:

the third voltage is substantially different than the first and second voltages.

3. A method as recited in claim 1 wherein:

the first, second, third, and fourth voltages are all substantially different in magnitude.

4. A method as recited in claim 1 wherein:

the fourth voltage is between the first and second voltages and offset by a first amount from the first voltage; and

the third voltage is between the first and second voltages and offset by a second amount from the second voltage.

5. A method as recited in claim 4 wherein:

the fourth voltage is closer to the first voltage than the second voltage; and

the third voltage is closer to the second voltage than the first voltage.

6. A method as recited in claim 4 wherein:

the first and second offsets are substantially equal in magnitude.

7. A method as recited in claim 4 wherein:

the first and second offsets are chosen so cumulative total leakage current through unselected memory cells is less than a programming current through the selected memory cell.

8. A method as recited in claim 4 wherein:

the first and second offsets are chosen so that cumulative leakage current through unselected memory cells is less than approximately one-half the programming current through the selected memory cell.

9. A method as recited in claim 1 wherein:

the at least some unselected X-lines and the at least some unselected Y-lines are biased before the selected X-line and selected Y-line are biased to the respective first and second voltages.

10. A method as recited in claim 1 wherein:

the at least some unselected X-lines and the at least some unselected Y-lines are biased at substantially the same time as the selected X-line and selected Y-line are biased.

11. A method as recited in claim 1 further comprising:

biasing the selected X line to the third voltage before it is biased to the first voltage; and

biasing the selected Y line to the fourth voltage before it is biased to the second voltage.

12. A method as recited in claim 1 wherein:

the memory cells comprise erasable memory cells.

13. A method as recited in claim 1 wherein each memory cell comprises:

a layer of organic material having a resistance that is switched to a lower or higher state by application of a voltage across the layer.

14. A method as recited in claim 1 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of memory cells.

15. A method as recited in claim 14 wherein:

the memory cells comprise anti-fuse memory cells.

16. A method as recited in claim 14 wherein:

the memory cells comprise fuse memory cells.

17. A method as recited in claim 1 wherein:

the memory cells comprise write-once memory cells.

18. A method as recited in claim 17 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of memory cells.

19. A method as recited in claim 18 wherein:

the memory cells comprise anti-fuse memory cells.

20. A method as recited in claim 18 wherein:

the memory cells comprise fuse memory cells.

21. A method as recited in claim 1 wherein:

the memory array comprises a three-dimensional memory array having at least two planes of write-once anti-fuse memory cells.

22. A method as recited in claim 14 further comprising:

for each memory plane adjacent to a selected memory plane having associated X-lines or Y-lines that are not also associated with the selected memory plane, biasing at least some of such adjacent plane X-lines not also associated with the selected memory plane to the third voltage, and at least some of such adjacent plane Y-lines not also associated with the selected memory plane to the fourth voltage.

23. A method as recited in claim 22 further comprising:

for each memory plane that is not adjacent to a selected memory plane, biasing at least some X-lines of such non-adjacent memory planes to the third voltage, and at least some of such non-adjacent Y-lines to the fourth voltage.

24. A method as recited in claim 22 further comprising:

for each memory plane that is not adjacent to a selected memory plane, allowing X-lines and Y-lines on such non-adjacent memory planes to float.

25. A method as recited in claim 9 further comprising:

allowing X-lines and Y-lines associated with non-selected memory planes that are not also associated with a selected memory plane to float.

26. A method as recited in claim 14 further comprising:

if a first memory plane adjacent to a selected memory plane is present having associated X-lines that are not also associated with the selected memory plane, biasing at least some of such adjacent plane X-lines to the third voltage; and

if a second memory plane adjacent to a selected memory plane is present having associated Y-lines that are not also associated with the selected memory plane, biasing at least some of such adjacent plane Y-lines to the fourth voltage.

27. In an integrated circuit including a three-dimensional array having at least two planes of write-once passive element memory cells, each memory cell respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of writing a selected memory cell coupled between a selected X-line and a selected Y-line associated with a selected memory plane, said method comprising the steps of:

biasing the selected X-line to a first voltage;

biasing the selected Y-line to a second voltage different than the first voltage;

biasing at least some unselected X-lines associated with the selected memory plane to a third voltage within a range defined by the first and second voltages; and

biasing at least some unselected Y-lines associated with the selected memory plane to a fourth voltage within the range defined by the first and second voltages and substantially different than the first and second voltages;

wherein the fourth voltage is closer to the first voltage than the second voltage and is offset by a first amount from the first voltage; and

the third voltage is closer to the second voltage than the first voltage and is offset by a second amount from the second voltage.

28. A method as recited in claim 27 further comprising:

for each memory plane adjacent to a selected memory plane having associated X-lines or Y-lines that are not also associated with the selected memory plane, biasing at least some of such adjacent plane X-lines not also associated with the selected memory plane to the third voltage, and at least some of such adjacent plane Y-lines not also associated with the selected memory plane to the fourth voltage.

29. A method as recited in claim 28 further comprising:

for each memory plane that is not adjacent to a selected memory plane, biasing at least some X-lines of such non-adjacent memory planes to the third voltage, and at least some of such non-adjacent Y-lines to the fourth voltage.

30. A method as recited in claim 28 further comprising:

for each memory plane that is not adjacent to a selected memory plane, allowing X-lines and Y-lines on such non-adjacent memory planes to float.

31. A method as recited in claim 27 further comprising:

allowing X-lines and Y-lines associated with non-selected memory planes that are not also associated with a selected memory plane to float.

32. A method as recited in claim 27 further comprising:

if a first memory plane adjacent to a selected memory plane is present having associated X-lines that are not also associated with the selected memory plane, biasing at least some of such adjacent plane X-lines to the third voltage; and

if a second memory plane adjacent to a selected memory plane is present having associated Y-lines that are not also associated with the selected memory plane, biasing at least some of such adjacent plane Y-lines to the fourth voltage.

33. In an integrated circuit including an array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of writing a selected memory cell coupled between a selected X-line and a selected Y-line, said method comprising the steps of:

biasing the selected X-line to a first voltage;

biasing the selected Y-line to a second voltage;

biasing at least some unselected X-lines to a third voltage; and

biasing at least some unselected Y-lines to a fourth voltage;

wherein the first, second, third, and fourth voltages are each substantially different.

34. In an integrated circuit including a memory array of passive element memory cells, each respectively coupled between a respective one of a plurality of X-lines and a respective one of a plurality of Y-lines, a method of programming a selected memory cell coupled between a selected X-line and a selected Y-line, said method comprising the steps of:

coupling the selected X-line and the selected Y-line to respective first and second voltage conveying nodes to impress a programming voltage across the selected memory cell connected therebetween; and

coupling at least some unselected X-lines and at least some unselected Y-lines to respective third and fourth voltage conveying nodes, each of the third and fourth voltages different in magnitude than the first and second voltages, to impress a particular voltage lower in magnitude than the programming voltage across the unselected memory cells connected respectively therebetween.

35. A method as recited in claim 34 wherein:

cumulative leakage current through unselected memory cells is supported more by current flow through the unselected X-lines and Y-lines than by current flow through the selected X-line and selected Y-line.

36. A method as recited in claim 34 wherein:

the fourth voltage is between the first and second voltages and offset by a first amount from the first voltage; and

the third voltage is between the first and second voltages and offset by a second amount from the second voltage.

37. A method as recited in claim 36 wherein:

the fourth voltage is closer to the first voltage than the second voltage; and

the third voltage is closer to the second voltage than the first voltage.

38. A method as recited in claim 37 wherein:

the first and second offsets are substantially equal in magnitude.

39. A method as recited in claim 36 wherein:

the first and second offsets are chosen so that cumulative leakage current through unselected memory cells is less than a programming current through the selected memory cell.

40. A method as recited in claim 39 wherein:

the first and second offsets are chosen so that cumulative leakage current through unselected memory cells is less than approximately one-half the programming current through the selected memory cell.

41. A method as recited in claim 36 wherein:

the first and second offsets are each chosen to be within the range of about 0.5 to 2.0 volts.

42. A method as recited in claim 34 wherein:

the memory array is a three-dimensional memory array having at least two planes of memory cells.

43. A method as recited in claim 34 wherein:

the memory cells are write-once anti-fuse memory cells.

44. In an integrated circuit including at least one memory sub-array of passive element memory cells, each memory cell within a given sub-array respectively coupled between a respective one of a plurality of X-lines associated with the given sub-array and a corresponding one of a plurality of Y-lines associated with the given sub-array, a method of programming memory cells comprising the steps of:

for each sub-array having at least one memory cell to be programmed;

biasing at least some X-lines within the sub-array to a write mode unselected X-line (UXL) voltage and biasing at least some Y-lines within the sub-array to a write mode unselected Y-line (UYL) voltage, both voltages chosen so that a particular voltage lower in magnitude than a programming voltage is impressed across the memory cells coupled respectively therebetween;

then

for each of a group of at least one memory cell within the sub-array to be programmed, pulsing its associated X-line to a write-mode selected X-line (SXL) voltage while pulsing its associated Y-line to a write-mode selected Y-line (SYL) voltage, both voltages chosen so that the programming voltage is impressed across the memory cell, for a time sufficient to program the memory cell.

45. A method as recited in claim 44 further comprising:

when no memory cells of the group remain to be programmed within the sub-array, then

biasing X-lines within the sub-array to an inactive X-line (IXL) voltage and biasing Y-lines within the sub-array to an inactive Y-line (IYL) voltage.

46. A method as recited in claim 44 wherein:

the particular voltage, when impressed across a memory cell, reverse biases the memory cell.

47. A method as recited in claim 44 wherein:

the programming voltage, when impressed across a memory cell, forward biases the memory cell.

48. A method as recited in claim 44 wherein:

at most only one sub-array is simultaneously taken into a write standby mode by biasing at least some X-lines within the sub-array to the UXL voltage and biasing at least some Y-lines within the sub-array to the UYL voltage.

49. A method as recited in claim 48 wherein:

at most only one selected memory cell which is coupled between a selected X-line and a selected Y-line within a sub-array is simultaneously programmed.

50. A method as recited in claim 48 wherein:

more than one selected memory cell along either a selected X-line or selected Y-line within a sub-array is simultaneously programmed.

51. A method as recited in claim 44 wherein:

more than one sub-array is simultaneously taken into a write standby mode by biasing at least some X-lines within each such sub-array to the UXL voltage and biasing at least some Y-lines within each such sub-array to the UYL voltage.

52. A method as recited in claim 51 wherein:

at most only one selected memory cell which is coupled between a selected X-line and a selected Y-line within a single sub-array is simultaneously programmed.

53. A method as recited in claim 51 wherein:

at least one selected memory cell within each of a plurality of sub-arrays are simultaneously programmed.

54. A method as recited in claim 44 wherein the biasing step comprises:

biasing at least a majority of the X-lines within the sub-array to the UXL voltage and biasing at least a majority of the Y-lines within the sub-array to the UYL voltage.

55. A method as recited in claim 44 wherein the biasing step comprises:

biasing at least substantially all the X-lines within the sub-array to the UXL voltage and biasing at least substantially all the Y-lines within the sub-array to the UYL voltage.

56. A method as recited in claim 44 wherein:

the memory cells comprises write-once anti-fuse memory cells.

57. A method as recited in claim 44 wherein:

the UYL voltage is between the SXL and SYL voltages and offset by a first amount from the SXL voltage; and

the UXL voltage is between the SXL and SYL voltages and offset by a second amount from the SYL voltage.

58. A method as recited in claim 57 wherein:

the first and second offsets are chosen so that cumulative leakage current through unselected memory cells is less than approximately one-half of a programming current through the selected memory cell.

59. A method as recited in claim 57 wherein:

the first and second offsets are each chosen to be within the range of about 0.5 to 2.0 volts.

60. In an integrated circuit including at least one three-dimensional memory sub-array of passive element memory cells arranged in at least two memory planes, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, a method of programming memory cells comprising the steps of:

for each memory plane within each sub-array having at least one memory cell to be programmed;

biasing at least some of the X-lines associated therewith to a write mode unselected X-line (UXL) voltage and biasing at least some of the Y-lines associated therewith to a write mode unselected Y-line (UYL) voltage, both voltages chosen so that a particular voltage lower in magnitude than a programming voltage is impressed across the memory cells coupled respectively therebetween;

then

for each of a group of at least one memory cell to be programmed within the memory plane and sub-array, pulsing its associated X-line to a write-mode selected X-line (SXL) voltage while pulsing its associated Y-line to a write-mode selected Y-line (SYL) voltage, both voltages chosen so that the programming voltage is impressed across the memory cell, for a time sufficient to program the memory cell,

wherein the programming voltage is greater in magnitude than the second voltage, and the second voltage is greater in magnitude than both the third and fourth voltages.

61. A method as recited in claim 60 further comprising:

when no memory cells of the group remain to be programmed within the sub-array, then biasing X-lines associated with the memory plane within the sub-array to an inactive X-line (IXL) voltage and biasing Y-lines associated with the memory plane within the sub-array to an inactive Y-line (IYL) voltage.

62. A method as recited in claim 60 wherein:

the particular voltage, when impressed across a memory cell, reverse biases the memory cell.

63. A method as recited in claim 60 wherein:

the programming voltage, when impressed across a memory cell, forward biases the memory cell.

64. A method as recited in claim 60 wherein:

at most only one sub-array is simultaneously taken into a write standby mode by biasing at least some X-lines within the sub-array to the UXL voltage and biasing at least some Y-lines within the sub-array to the UYL voltage.

65. A method as recited in claim 64 wherein:

at most only one selected memory cell which is coupled between a selected X-line and a selected Y-line within a sub-array is simultaneously programmed.

66. A method as recited in claim 64 wherein:

more than one selected memory cell along either a selected X-line or selected Y-line within a sub-array is simultaneously programmed.

67. A method as recited in claim 64 wherein:

at least one selected memory cell associated with each of at least two memory planes within a sub-array is simultaneously programmed.

68. A method as recited in claim 60 wherein:

more than one sub-array is simultaneously taken into a write standby mode by biasing at least some X-lines within each such sub-array to the UXL voltage and biasing at least some Y-lines within each such sub-array to the UYL voltage.

69. A method as recited in claim 68 wherein:

at most only one selected memory cell which is coupled between a selected X-line and a selected Y-line within a single sub-array is simultaneously programmed.

70. A method as recited in claim 68 wherein:

at least one selected memory cell within each of a plurality of sub-arrays are simultaneously programmed.

71. A method as recited in claim 60 wherein the biasing step comprises:

biasing at least a majority of the X-lines associated with a memory plane and sub-array to the UXL voltage and biasing at least a majority of the Y-lines associated with the memory plane and sub-array to the UYL voltage.

72. A method as recited in claim 60 wherein the biasing step comprises:

biasing at least substantially all the X-lines associated with a memory plane and sub-array to the UXL voltage and biasing at least substantially all the Y-lines associated with the memory plane and sub-array to the UYL voltage.

73. A method as recited in claim 60 wherein:

each passive element memory cell is forward biased in a direction from its associated X-line to its associated Y-line;

each X-line is associated with memory cells within a memory plane above the X-line, if such memory plane is present, and is further associated with memory cells within a memory plane below the X-line, if such memory plane is present; and

each Y-line is associated with memory cells within a memory plane above the Y-line, if such memory plane is present, and is further associated with memory cells within a memory plane below the Y-line, if such memory plane is present.

74. A method as recited in claim 60 wherein:

each passive element memory cell within at least a first memory plane is forward biased in a direction from its associated X-line to its associated Y-line;

each passive element memory cell within at least a second memory plane adjacent to the first memory plane is forward biased in a direction from its associated Y-line to its associated X-line;

each X-line is associated with memory cells within a memory plane above the X-line, if such memory plane is present, and is further associated with memory cells within a memory plane below the X-line, if such memory plane is present; and

each Y-line is associated with memory cells within a memory plane above the Y-line, if such memory plane is present, and is further associated with memory cells within a memory plane below the Y-line, if such memory plane is present.

75. An integrated circuit comprising:

an array of passive element memory cells, each respectively having a first terminal coupled to a respective one of a plurality of X-lines and having a second terminal coupled to a respective one of a plurality of Y-lines;

a first array support circuit for biasing each X line, when selected during a write mode of operation, to a first voltage and when unselected during a write mode of operation, to a third voltage;

a second array support circuit for biasing each Y line, when selected during a write mode of operation, to a second voltage and when unselected during a write mode of operation, to a fourth voltage;

wherein the first voltage is different than the second voltage;

wherein the third voltage falls within a range defined by the first and second voltages; and

wherein the fourth voltage falls within the range defined by the first and second voltages and is substantially different than the first and second voltages.

76. An integrated circuit comprising:

at least one memory sub-array of passive element memory cells arranged in at least one memory plane, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, each of the memory cells having a directionality from a respective first terminal to a respective second terminal thereof;

array circuitry configured, during a write mode of operation, for biasing the respective first terminal of each selected memory cell within a selected memory plane of a selected sub-array to a first voltage, for biasing the respective second terminal of each selected memory cell within a selected memory plane of a selected sub-array to a second voltage different than the first voltage, for biasing the respective first terminal of at least a group of unselected memory cells within a selected memory plane of a selected sub-array to a third voltage having a value within a range defined by the first and second voltages, and for biasing the respective second terminal of at least a group of unselected memory cells within a selected memory plane of a selected sub-array to a fourth voltage having a value within the range defined by the first and second voltages and substantially different than the first and second voltages.

77. An integrated circuit as recited in claim 76 wherein the array circuitry comprises:

X-line circuitry configured, during a write mode of operation, for biasing each selected X-line to the first voltage if such selected X-line is coupled to the first terminal of a selected memory cell, and to the second voltage if each selected X-line is coupled to the second terminal of a selected memory cell, and for biasing each unselected X-line to the third voltage if such unselected X-line is connected to the respective first terminal of unselected memory cells within a selected memory plane, and to the fourth voltage if such unselected X-line is connected to the respective second terminal of unselected memory cells within a selected memory plane; and

Y-line circuitry configured, during a write mode of operation, for biasing each selected Y-line to the first voltage if such selected Y-line is coupled to the first terminal of a selected memory cell, and to the second voltage if such selected Y-line is coupled to the second terminal of a selected memory cell, and for biasing each unselected Y-line to the third voltage if such unselected Y-line is connected to the respective first terminal of unselected memory cells within a selected memory plane, and to the fourth voltage if such unselected Y-line is connected to the respective second terminal of unselected memory cells within a selected memory plane.

78. An integrated circuit comprising:

at least one memory sub-array of passive element memory cells arranged in at least one memory plane, each memory cell of a given memory plane within a given sub-array respectively coupled to a respective one of a plurality of X-lines associated with the given memory plane and given sub-array, and further coupled to a corresponding one of a plurality of Y-lines associated with the given memory plane and given sub-array, each of the memory cells having a directionality from a respective first terminal to a respective second terminal thereof; and

array circuitry configured, during a write mode of operation for a selected memory plane of a selected sub-array, for impressing a programming voltage in a forward-biased direction across a selected memory cell therewithin, for impressing a second voltage in a reverse-biased direction across unselected memory cells therewithin, for impressing a third voltage in a forward-biased direction across half-selected memory cells coupled to a selected X-line therewithin, and for impressing a fourth voltage in a forward-biased direction across half-selected memory cells coupled to a selected Y-line therewithin;

wherein the programming voltage is greater in magnitude than the second voltage, and the second voltage is greater in magnitude than both the third and fourth voltages.