Semiconductor memory device with redundancy

• US 6,618,299 B2
• Filed: 09/05/2001
• Issued: 09/09/2003
• Est. Priority Date: 01/04/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Sohn, Kyo-Min, Suh, Young-Ho
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US09/946,744
• Publication Number:
  US 20020086449A1
• Time in Patent Office: 734 Days
• Field of Search: 365/200, 365/196, 365/230.02, 365/189.02, 365/230.03, 365/230.06, 365/231, 365/191
• US Class Current: 365/200
• CPC Class Codes: G11C 29/80 with improved layout
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.

Claims

1. A semiconductor memory device, comprising:

a default array block comprising a default array and sense amplifier;

a row redundant array block, independent of the default array, comprising row redundant arrays for compensating for a deficiency in a row direction;

a column redundant array block, independent of the default array, comprising column redundant arrays for compensating for deficiency in a column direction;

a controller for generating a first control signal that is commonly applied to the default array, row redundant array block, and column redundant array block; and

a redundant calculation circuit, responsive to the first control signal and an address signal, for generating a second control signal to the row and column redundant array blocks and to determine whether a redundant array is accessed, and for generating a third control signal to disable the sense amplifier of the default array during a redundant array access.

2. The semiconductor memory device of claim 1, wherein the row redundant array block and the column redundant array block each comprise a sense amplifier, a word line driver, and a decoder.

3. The semiconductor memory device of claim 1, wherein the row redundant array block, the column redundant array block and the default array block share a common data line.

4. The semiconductor memory device of claim 1, further comprising a multiplexer, operatively connected to data lines of the row redundant array block, data lines of the column redundant array block and data lines of the default array block, to selectively output signals from the row redundant array block, column redundant array block and the default array block.

5. The semiconductor memory device of claim 1, wherein the row redundant arrays are mapped so that column addresses of the default array become row addresses, and the column redundant arrays are mapped so that a portion of the row addresses of the default array become column addresses.

6. A semiconductor memory device, comprising:

a default array;

a row redundant array block comprising row redundant arrays that are independent from the default array, for supplementing a deficiency in a row direction, wherein the row redundant array block is mapped so that the column addresses of the default array become row addresses; and

a column redundant array block comprising column redundant arrays that are independent from the default array, for supplementing a deficiency in a column direction, wherein the column redundant array block is mapped so that a portion of the row addresses of the default array become column addresses.

7. The semiconductor memory device of claim 6, further comprising a redundancy calculation circuit for generating a control signal to disable a sense amplifier of the default array during a redundant array access.

9. The semiconductor memory device of claim 6, wherein the row redundant array block, the column redundant array block and the default array share a common data line.

10. The semiconductor memory device of claim 6, further comprising a multiplexer, operatively connected to data lines of row redundant array block, data lines of the column redundant array block and data lines of the default array, to selectively output signals from the row redundant array block, column redundant array block and the default array.

8. The semiconductor memory device of 6, wherein the row redundant array block and the column redundant array block each comprise a sense amplifier, a word line driver, and a decoder.

11. A method for managing a memory array in a semiconductor memory device, wherein the memory array comprises a default array and a redundant array of memory cells, the method comprising the steps of:

mapping a row redundant array so that column addresses of the default array become row addresses;

accessing the row redundant array to compensate for a deficiency in a row direction of the default array;

mapping a column redundant array so that a portion of row addresses of the default array become column addresses;

accessing the column redundant array to compensate for a deficiency in a column direction of the default array; and

disabling operation of a sense amplifier of the default array during an access of one of the row redundant array and column redundant array.

12. The method of claim 11, further comprising the step of outputting data from the row redundant array, column redundant array and default array to a common data line.

13. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for managing a memory array in a semiconductor memory device, wherein the memory array comprises a default array and a redundant array of memory cells, the method steps comprising:

mapping a row redundant array so that column addresses of the default array become row addresses;

accessing the row redundant array to compensate for a deficiency in a row direction of the default array;

mapping a column redundant array so that a portion of row addresses of the default array become column addresses;

accessing the column redundant array to compensate for a deficiency in a column direction of the default array; and

disabling operation of a sense amplifier of the default array during an access of one of the row redundant array and column redundant array.